TMS320VC5407 datasheet(76/110 Pages) TI

76 / 110 page

Electrical Specifications

November 2001 − Revised April 2004

SPRS007D

5.8

Memory and Parallel I/O Interface Timing

5.8.1 Memory Read

External memory reads can be performed in consecutive or nonconsecutive mode under control of the

CONSEC bit in the BSCR. Table 5−8 and Table 5−9 assume testing over recommended operating conditions

with MSTRB = 0 and H = 0.5tc(CO) (see Figure 5−5 and Figure 5−6).

Table 5−8. Memory Read Timing Requirements

MIN

MAX

UNIT

Access time, read data access from address

For accesses not immediately following a

HOLD operation

4H−9

ta(A)M1

Access time, read data access from address

valid, first read access†

For read accesses immediately following a

HOLD operation

4H−11

ta(A)M2

Access time, read data access from address valid, consecutive read accesses†

2H−9

tsu(D)R

Setup time, read data valid before CLKOUT low

th(D)R

Hold time, read data valid after CLKOUT low

† Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.

Table 5−9. Memory Read Switching Characteristics

PARAMETER

MIN

MAX

UNIT

Delay time CLKOUT low to address valid†

For accesses not immediately following a

HOLD operation

− 1

td(CLKL-A)

Delay time, CLKOUT low to address valid†

For read accesses immediately following a

HOLD operation

− 1

td(CLKL-MSL)

Delay time, CLKOUT low to MSTRB low

− 1

td(CLKL-MSH)

Delay time, CLKOUT low to MSTRB high

† Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.

TMS320VC5407 Datasheet(PDF) 76 Page - Texas Instruments

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