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TMS320VC5407 Datasheet(PDF) 93 Page - Texas Instruments |
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TMS320VC5407 Datasheet(HTML) 93 Page - Texas Instruments |
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93 / 110 page ![]() Electrical Specifications 93 November 2001 − Revised April 2004 SPRS007D Table 5−22. McBSP Transmit and Receive Switching Characteristics† PARAMETER MIN MAX UNIT tc(BCKRX) Cycle time, BCLKR/X BCLKR/X int 4P‡ ns tw(BCKRXH) Pulse duration, BCLKR/X high BCLKR/X int D − 1§ D + 1§ ns tw(BCKRXL) Pulse duration, BCLKR/X low BCLKR/X int C − 1§ C + 1§ ns t Delay time BCLKR high to internal BFSR valid BCLKR int − 3 3 ns td(BCKRH-BFRV) Delay time, BCLKR high to internal BFSR valid BCLKR ext 0 12 ns t Delay time BCLKX high to internal BFSX valid BCLKX int − 1 5 ns td(BCKXH-BFXV) Delay time, BCLKX high to internal BFSX valid BCLKX ext 2 10 ns t Disable time, BCLKX high to BDX high impedance following last data BCLKX int 6 ns tdis(BCKXH-BDXHZ) Disable time, BCLKX high to BDX high impedance following last data bit of transfer BCLKX ext 10 ns t Delay time BCLKX high to BDX valid DXENA 0# BCLKX int − 1¶ 10 ns td(BCKXH-BDXV) Delay time, BCLKX high to BDX valid DXENA = 0# BCLKX ext 2 20 ns t Delay time, BFSX high to BDX valid BFSX int −1¶ 7 ns td(BFXH-BDXV) Delay time, BFSX high to BDX valid ONLY applies when in data delay 0 (XDATDLY = 00b) mode BFSX ext 2 11 ns † CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ P = 0.5 * processor clock § T = BCLKRX period = (1 + CLKGDV) * 2P C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even ¶ Minimum delay times also represent minimum output hold times. # The transmit delay enable (DXENA) feature of the McBSP is not implemented on the TMS320VC5407/TMS320VC5404. Bit(n-1) (n-2) (n-3) BCLKR BFSR (int) BFSR (ext) BDR tw(BCKRXH) tc(BCKRX) tw(BCKRXL) td(BCKRH-BFRV) td(BCKRH-BFRV) tsu(BFRH-BCKRL) th(BCKRL-BFRH) th(BCKRL-BDRV) tsu(BDRV-BCKRL) tr(BCKRX) tf(BCKRX) Figure 5−21. McBSP Receive Timings |
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