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TMS320VC5407 Datasheet(PDF) 61 Page - Texas Instruments |
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TMS320VC5407 Datasheet(HTML) 61 Page - Texas Instruments |
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61 / 110 page ![]() Functional Overview 61 November 2001 − Revised April 2004 SPRS007D 3.16 Memory-Mapped Registers The 5407/5404 has 27 memory-mapped CPU registers, which are mapped in data memory space address 0h to 1Fh. Each 5407/5404 device also has a set of memory-mapped registers associated with peripherals. Table 3−23 gives a list of CPU memory-mapped registers (MMRs) available on 5407/5404. Table 3−24 shows additional peripheral MMRs associated with the 5407/5404. Table 3−23. CPU Memory-Mapped Registers NAME ADDRESS DESCRIPTION NAME DEC HEX DESCRIPTION IMR 0 0 Interrupt mask register IFR 1 1 Interrupt flag register — 2−5 2−5 Reserved for testing ST0 6 6 Status register 0 ST1 7 7 Status register 1 AL 8 8 Accumulator A low word (15−0) AH 9 9 Accumulator A high word (31−16) AG 10 A Accumulator A guard bits (39−32) BL 11 B Accumulator B low word (15−0) BH 12 C Accumulator B high word (31−16) BG 13 D Accumulator B guard bits (39−32) TREG 14 E Temporary register TRN 15 F Transition register AR0 16 10 Auxiliary register 0 AR1 17 11 Auxiliary register 1 AR2 18 12 Auxiliary register 2 AR3 19 13 Auxiliary register 3 AR4 20 14 Auxiliary register 4 AR5 21 15 Auxiliary register 5 AR6 22 16 Auxiliary register 6 AR7 23 17 Auxiliary register 7 SP 24 18 Stack pointer register BK 25 19 Circular buffer size register BRC 26 1A Block repeat counter RSA 27 1B Block repeat start address REA 28 1C Block repeat end address PMST 29 1D Processor mode status (PMST) register XPC 30 1E Extended program page register — 31 1F Reserved |
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