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TMS320VC5407 Datasheet(PDF) 75 Page - Texas Instruments

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Part # TMS320VC5407
Description  Fixed-Point Digital Signal Processors
PDF  110 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320VC5407 Datasheet(HTML) 75 Page - Texas Instruments

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Electrical Specifications
75
November 2001 − Revised April 2004
SPRS007D
5.7.2 Multiply-By-N Clock Option (PLL Enabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to
generate the internal machine cycle. The selection of the clock mode and the value of N is described in
Section 3.10. Following reset, the software PLL can be programmed for the desired multiplication factor. Refer
to the TMS320C54x DSP Reference Set, Volume 1: CPU and Peripherals (literature number SPRU131) for
detailed information on programming the PLL.
When an external clock source is used, the external frequency injected must conform to specifications listed
in Table 5−6.
Table 5−6 and Table 5−7 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 5−4).
Table 5−6. Multiply-By-N Clock Option Timing Requirements
MIN
MAX
UNIT
Integer PLL multiplier N (N = 1−15)†
20
200
tc(CI)
Cycle time, X2/CLKIN
PLL multiplier N = x.5†
20
100
ns
tc(CI)
Cycle time, X2/CLKIN
PLL multiplier N = x.25, x.75†
20
50
ns
tf(CI)
Fall time, X2/CLKIN
4
ns
tr(CI)
Rise time, X2/CLKIN
4
ns
tw(CIL)
Pulse duration, X2/CLKIN low
4
ns
tw(CIH)
Pulse duration, X2/CLKIN high
4
ns
† N is the multiplication factor.
Table 5−7. Multiply-By-N Clock Option Switching Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
tc(CO)
Cycle time, CLKOUT
8.33
ns
td(CI-CO)
Delay time, X2/CLKIN high/low to CLKOUT high/low
4
7
11
ns
tf(CO)
Fall time, CLKOUT
2
ns
tr(CO)
Rise time, CLKOUT
2
ns
tw(COL)
Pulse duration, CLKOUT low
H
ns
tw(COH)
Pulse duration, CLKOUT high
H
ns
tp
Transitory phase, PLL lock-up time
30
ms
tc(CO)
tc(CI)
tw(COH)
tf(CO)
tr(CO)
tf(CI)
X2/CLKIN
CLKOUT
td(CI-CO)
tw(COL)
tr(CI)
tp
Unstable
tw(CIH)
tw(CIL)
NOTE A: The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as 00 (CLKOUT not
divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.
Figure 5−4. Multiply-by-One Clock Timing



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