TMS320VC5407 datasheet(59/110 Pages) TI

59 / 110 page

Functional Overview

November 2001 − Revised April 2004

SPRS007D

3.13.10.1 Receiver Buffer Register (RBR)

The UART receiver section consists of a receiver shift register (RSR) and a RBR. The RBR is actually a 16-byte

FIFO. Timing is supplied by the 16× receiver clock. Receiver section control is a function of the UART line control

The UART RSR receives serial data from SIN. The RSR then concatenates the data and moves it into the RBR

FIFO. In the TL16C450 mode, when a character is placed in the RBR and the received data available interrupt

is enabled (IER0 = 1), an interrupt is generated. This interrupt is cleared when the data is read out of the RBR.

In the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register.

3.13.10.2 Scratch Register

The scratch register is an 8-bit register that is intended for the programmer’s use as a scratchpad in the sense

that it temporarily holds the programmer’s data without affecting any other UART operation.

3.13.10.3 Transmitter Holding Register (THR)

The UART transmitter section consists of a THR and a transmitter shift register (TSR). The THR is actually a

16-byte FIFO. Transmitter section control is a function of the UART line control register.

The UART THR receives data off the internal data bus and when the shift register is idle, moves it into the TSR.

The TSR serializes the data and outputs it at SOUT. In the TL16C450 mode, if the THR is empty and the

transmitter holding register empty (THRE) interrupt is enabled (IER1 = 1), an interrupt is generated. This

interrupt is cleared when a character is loaded into the register. In the FIFO mode, the interrupts are generated

based on the control setup in the FIFO control register.

3.14 General-Purpose I/O Pins

In addition to the standard BIO and XF pins, the 5407/5404 has pins that can be configured for

general-purpose I/O. These pins are:

•

16 McBSP pins — BCLKX0/1, BCLKR0/1, BDR0/1/2, BFSX0/1, BFSR0/1, BDX0/1/2, BCLKRX2,

BFSRX2

•

8 HPI data pins — HD0−HD7

The general-purpose I/O function of these pins is only available when the primary pin function is not required.

3.14.1

McBSP Pins as General-Purpose I/O

When the receive or transmit portion of a McBSP is in reset, its pins can be configured as general-purpose

inputs or outputs. For more details on this feature, see Section 3.8.

3.14.2

HPI Data Pins as General-Purpose I/O

The 8-bit bidirectional data bus of the HPI can be used as general-purpose input/output (GPIO) pins when the

HPI is disabled (HPIENA = 0) or when the HPI is used in HPI16 mode (HPI16 = 1). Two memory-mapped

registers are used to control the GPIO function of the HPI data pins — the general-purpose I/O control register

(GPIOCR) and the general-purpose I/O status register (GPIOSR). The GPIOCR is shown in Figure 3−23.

TOUT1

Reserved

R/W-0

DIR7

DIR6

DIR5

DIR4

DIR3

DIR2

DIR1

DIR0

R/W-0

LEGEND: R = Read, W = Write, n = value after reset

Figure 3−23. General-Purpose I/O Control Register (GPIOCR) [MMR Address 003Ch]

TMS320VC5407 Datasheet(PDF) 59 Page - Texas Instruments

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