TMS320VC5407 datasheet(55/110 Pages) TI

55 / 110 page

Functional Overview

November 2001 − Revised April 2004

SPRS007D

When an interrupt is generated, the IIR indicates that an interrupt is pending and encodes the type of interrupt

in its three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 3−15

and described in Table 3−17. Detail on each bit is as follows:

•

Bit 0: This bit is used either in a hardwire prioritized or polled interrupt system. When bit 0 is cleared, an

interrupt is pending If bit 0 is set, no interrupt is pending.

•

Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in Table 3−15

•

Bit 3: This bit is always cleared in TL16C450 mode. In FIFO mode, bit 3 is set with bit 2 to indicate that a

time-out interrupt is pending.

•

Bits 4 and 5: These two bits are not used (always cleared).

•

Bits 6 and 7: These bits are always cleared in TL16C450 mode. They are set when bit 0 of the FIFO control

Table 3−17. Interrupt Control Functions

INTERRUPT

IDENTIFICATION REGISTER

PRIORITY

LEVEL

INTERRUPT TYPE

INTERRUPT SOURCE

INTERRUPT RESET

METHOD

BIT 3

BIT 2 BIT 1 BIT 0

LEVEL

INTERRUPT TYPE

INTERRUPT SOURCE

METHOD

None

Receiver line status

Overrun error, parity error,

framing error, or break interrupt

Read the line status register

Received data available

Receiver data available in the

TL16C450 mode or trigger level

reached in the FIFO mode

Read the receiver buffer register

Character time-out

indication

characters

have

been

removed from or input to the

receiver FIFO during the last four

character times, and there is at

least one character in it during

this time

Read the receiver buffer register

Transmitter holding

Transmitter

holding

empty

Read the interrupt identification

writing into the transmitter

holding register

3.13.7

Line Control Register (LCR)

The system programmer controls the format of the asynchronous data communication exchange through the

LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates

the need for separate storage of the line characteristics in system memory. The contents of this register are

summarized in Table 3−15 and described in the following bulleted list.

•

Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character.

These bits are encoded as shown in Table 3−18.

Table 3−18. Serial Character Word Length

BIT 1

BIT 0

WORD LENGTH

5 bits

6 bits

7 bits

8 bits

•

Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When

bit 2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated

is dependent on the word length selected with bits 0 and 1. The receiver clocks only the first stop bit

regardless of the number of stop bits selected. The number of stop bits generated in relation to word length

and bit 2 are shown in Table 3−19.

TMS320VC5407 Datasheet(PDF) 55 Page - Texas Instruments

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