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TMS320VC5407 Datasheet(PDF) 66 Page - Texas Instruments

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Part # TMS320VC5407
Description  Fixed-Point Digital Signal Processors
PDF  110 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320VC5407 Datasheet(HTML) 66 Page - Texas Instruments

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Functional Overview
66
November 2001 − Revised April 2004
SPRS007D
3.19 Interrupts
Vector-relative locations and priorities for all internal and external interrupts are shown in Table 3−27.
Table 3−27. Interrupt Locations and Priorities
NAME
LOCATION
DECIMAL
HEX
PRIORITY
FUNCTION
RS, SINTR
0
00
1
Reset (hardware and software reset)
NMI, SINT16
4
04
2
Nonmaskable interrupt
SINT17
8
08
—
Software interrupt #17
SINT18
12
0C
—
Software interrupt #18
SINT19
16
10
—
Software interrupt #19
SINT20
20
14
—
Software interrupt #20
SINT21
24
18
—
Software interrupt #21
SINT22
28
1C
—
Software interrupt #22
SINT23
32
20
—
Software interrupt #23
SINT24
36
24
—
Software interrupt #24
SINT25
40
28
—
Software interrupt #25
SINT26
44
2C
—
Software interrupt #26
SINT27
48
30
—
Software interrupt #27
SINT28
52
34
—
Software interrupt #28
SINT29
56
38
—
Software interrupt #29
SINT30
60
3C
—
Software interrupt #30
INT0, SINT0
64
40
3
External user interrupt #0
INT1, SINT1
68
44
4
External user interrupt #1
INT2, SINT2
72
48
5
External user interrupt #2
TINT0, SINT3
76
4C
6
Timer 0 interrupt
BRINT0, SINT4
80
50
7
McBSP #0 receive interrupt
BXINT0, SINT5
84
54
8
McBSP #0 transmit interrupt
BRINT2, SINT6
88
58
9
McBSP #2 receive interrupt (default)†
BXINT2, SINT7
92
5C
10
McBSP #2 transmit interrupt (default)†
INT3, TINT1, SINT8
96
60
11
External user interrupt #3/Timer 1 interrupt‡
HINT, SINT9
100
64
12
HPI interrupt
BRINT1, SINT10
104
68
13
McBSP #1 receive interrupt (default)†
BXINT1, SINT11
108
6C
14
McBSP #1 transmit interrupt (default)†
DMAC4,SINT12
112
70
15
DMA channel 4
DMAC5,SINT13
116
74
16
DMA channel 5
UART, SINT14
120
78
—
UART interrupt
Reserved
124−127
7C−7F
—
Reserved
† See Table 3−13 for other interrupt selections.
‡ The INT3 and TINT1 interrupts are ORed together. To distinguish one from the other, one of these two interrupt sources must be inhibited.



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