 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TMS320VC5407 Datasheet(PDF) 62 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
TMS320VC5407 Datasheet(HTML) 62 Page - Texas Instruments |
|
|
62 / 110 page  Functional Overview 62 November 2001 − Revised April 2004 SPRS007D Table 3−24. Peripheral Memory-Mapped Registers for Each DSP Subsystem NAME ADDRESS DESCRIPTION NAME DEC HEX DESCRIPTION DRR20 32 20 McBSP 0 Data Receive Register 2 DRR10 33 21 McBSP 0 Data Receive Register 1 DXR20 34 22 McBSP 0 Data Transmit Register 2 DXR10 35 23 McBSP 0 Data Transmit Register 1 TIM 36 24 Timer 0 Register PRD 37 25 Timer 0 Period Register TCR 38 26 Timer 0 Control Register — 39 27 Reserved SWWSR 40 28 Software Wait-State Register BSCR 41 29 Bank-Switching Control Register — 42 2A Reserved SWCR 43 2B Software Wait-State Control Register HPIC 44 2C HPI Control Register (HMODE = 0 only) — 45−47 2D−2F Reserved DRR22 48 30 McBSP 2 Data Receive Register 2 DRR12 49 31 McBSP 2 Data Receive Register 1 DXR22 50 32 McBSP 2 Data Transmit Register 2 DXR12 51 33 McBSP 2 Data Transmit Register 1 SPSA2 52 34 McBSP 2 Subbank Address Register† SPSD2 53 35 McBSP 2 Subbank Data Register† — 54−55 36−37 Reserved SPSA0 56 38 McBSP 0 Subbank Address Register† SPSD0 57 39 McBSP 0 Subbank Data Register† — 58−59 3A−3B Reserved GPIOCR 60 3C General-Purpose I/O Control Register GPIOSR 61 3D General-Purpose I/O Status Register CSIDR 62 3E Device ID Register — 63 3F Reserved DRR21 64 40 McBSP 1 Data Receive Register 2 DRR11 65 41 McBSP 1 Data Receive Register 1 DXR21 66 42 McBSP 1 Data Transmit Register 2 DXR11 67 43 McBSP 1 Data Transmit Register 1 USAR 68 44 UART Subbank Address Register USDR 69 45 UART Subbank Data Register — 70−71 46−47 Reserved SPSA1 72 48 McBSP 1 Subbank Address Register† SPSD1 73 49 McBSP 1 Subbank Data Register† — 74−75 4A−4B Reserved TIM1 76 4C Timer 1 Register PRD1 77 4D Timer 1 Period Register TCR1 78 4E Timer 1 Control Register — 79−83 4F−53 Reserved DMPREC 84 54 DMA Priority and Enable Control Register DMSA 85 55 DMA Subbank Address Register‡ DMSDI 86 56 DMA Subbank Data Register with Autoincrement‡ DMSDN 87 57 DMA Subbank Data Register‡ CLKMD 88 58 Clock Mode Register (CLKMD) — 89−95 59−5F Reserved † See Table 3−25 for a detailed description of the McBSP control registers and their subaddresses. ‡ See Table 3−26 for a detailed description of the DMA subbank addressed registers. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
