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TMS320VC5407 Datasheet(PDF) 60 Page - Texas Instruments |
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TMS320VC5407 Datasheet(HTML) 60 Page - Texas Instruments |
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60 / 110 page  Functional Overview 60 November 2001 − Revised April 2004 SPRS007D The direction bits (DIRx) are used to configure HD0−HD7 as inputs or outputs (0 = input, 1 = output). Bit 15 of the GPIOCR is also used as the Timer1 output enable bit, TOUT1. The TOUT1 bit enables or disables the Timer1 output on the HINT/TOUT1 pin. If TOUT1 = 0, the Timer1 output is not available externally; if TOUT1 = 1, the Timer1 output is driven on the HINT/TOUT1 pin. Note also that the Timer1 output is only available when the HPI is disabled (HPIENA input pin = 0). The status of the GPIO pins can be monitored using the bits of the GPIOSR. The GPIOSR is shown in Figure 3−24. When read, these bits reflect the state of the input pins, and when written, determine the state of outputs. 15 8 Reserved 0 7 43 0 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R = Read, W = Write, n = value after reset Figure 3−24. General-Purpose I/O Status Register (GPIOSR) [MMR Address 003Dh] 3.15 Device ID Register A read-only memory-mapped register has been added to the 5407/5404 to allow user application software to identify on which device the program is being executed. 15 8 Chip ID R 7 43 0 Chip Revision SUBSYSID RR LEGEND: R = Read, W = Write Figure 3−25. Device ID Register (CSIDR) [MMR Address 003Eh] Table 3−22. Device ID Register (CSIDR) Bit Functions BIT NO. BIT NAME FUNCTION 15−8 Chip ID Chip identification (hex code of 06 for 5407 and 03 for 5404) 7−4 Chip Revision Chip revision identification 3−0 SUBSYSID Subsystem identification (0000b for single core devices) |
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