TMS320VC5407 datasheet(23/110 Pages) TI

23 / 110 page

Functional Overview

November 2001 − Revised April 2004

SPRS007D

Functional Overview

The following functional overview is based on the block diagram in Figure 3−1.

UART

GPIO

MBus

40K RAM

Dual Access

Program/Data†

McBSP0

McBSP1

McBSP2

RHEA Bus

APLL

TIMER

JTAG

Clocks

RHEAbus

RHEA

Bridge

TI BUS

xDMA

logic

128K Program

ROM‡

Enhanced XIO

P, C, D, E Buses and Control Signals

XIO

16HPI

54X cLEAD

16 HPI

† 16K for 5404

‡ 64K for 5404

Figure 3−1. TMS320VC5407/TMS320VC5404 Functional Block Diagram

3.1

Memory

The 5407/5404 device provides both on-chip ROM and RAM memories to aid in system performance and

integration.

3.1.1 Data Memory

The data memory space addresses up to 64K of 16-bit words. The device automatically accesses the on-chip

RAM when addressing within its bounds. When an address is generated outside the RAM bounds, the device

automatically generates an external access.

The advantages of operating from on-chip memory are as follows:

•

Higher performance because no wait states are required

•

Higher performance because of better flow within the pipeline of the central arithmetic logic unit (CALU)

•

Lower cost than external memory

•

Lower power than external memory

The advantage of operating from off-chip memory is the ability to access a larger address space.

TMS320VC5407 Datasheet(PDF) 23 Page - Texas Instruments

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