TMS320VC5407 datasheet(57/110 Pages) TI

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Functional Overview

November 2001 − Revised April 2004

SPRS007D

•

Bit 4‡: This bit is the break interrupt (BI) indicator. When BI is set, it indicates that the received data input

was held low for longer than a full-word transmission time. A full-word transmission time is defined as the

total time to transmit the start, data, parity, and stop bits. BI is cleared every time the CPU reads the contents

of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it

applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. When a

break occurs, only one 0 character is loaded into the FIFO. The next character transfer is enabled after SIN

goes to the marking state for at least two RCLK samples and then receives the next valid start bit.

•

Bit 5: This bit is the THRE indicator. THRE is set when the THR is empty, indicating that the UART is ready

to accept a new character. If the THRE interrupt is enabled when THRE is set, an interrupt is generated.

THRE is set when the contents of the THR are transferred to the TSR. THRE is cleared concurrent with the

loading of the THR by the CPU. In the FIFO mode, THRE is set when the transmit FIFO is empty; it is cleared

when at least one byte is written to the transmit FIFO.

•

Bit 6: This bit is the transmitter empty (TEMT) indicator. TEMT bit is set when the THR and the TSR are

both empty. When either the THR or the TSR contains a data character, TEMT is cleared. In the FIFO mode,

TEMT is set when the transmitter FIFO and shift register are both empty.

•

Bit 7: In the TL16C550C mode, this bit is always cleared. In the TL16C450 mode, this bit is always cleared.

In the FIFO mode, LSR7 is set when there is at least one parity, framing, or break error in the FIFO. It is

cleared when the microprocessor reads the LSR and there are no subsequent errors in the FIFO.

3.13.9

Modem Control Register (MCR)

The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device. On the UART

peripheral, only one bit is active in this register

•

Bit 4: This bit (LOOP) provides a local loop back feature for diagnostic testing of the UART. When LOOP

is set, the following occurs:

−

The transmitter SOUT is set high.

−

The receiver SIN is disconnected.

−

The output of the TSR is looped back into the receiver shift register input.

3.13.10 Programmable Baud Generator

The UART contains a programmable baud generator that takes a clock input in the range between DC and

16 MHz and divides it by a divisor in the range between 1 and (216−1). The output frequency of the baud

generator is sixteen times (16×) the baud rate. The formula for the divisor is:

divisor = XIN frequency input ÷ (desired baud rate × 16)

Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must

be loaded during initialization of the UART in order to ensure desired operation of the baud generator. When

either of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.

Table 3−20 and Table 3−21 illustrate the use of the baud generator with clock frequencies of 1.8432 MHz and

3.072 MHz respectively. For baud rates of 38.4 kbits/s and below, the error obtained is very small. The accuracy

of the selected baud rate is dependent on the selected clock frequency.

‡ Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.

TMS320VC5407 Datasheet(PDF) 57 Page - Texas Instruments

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