TMS320DM642 datasheet(108/178 Pages) TI

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HOLD

HOLDA

EMIF Bus (A)

DSP Owns Bus

External Requestor

Owns Bus

DSP Owns Bus

DM642

AECLKOUTx(B)

(EKxHZ = 0)

AECLKOUTx(B)

(EKxHZ = 1)

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200J – JULY 2002 – REVISED AUGUST 2005

5.8.3.4

HOLD/HOLDA Timing

Table 5-28. Timing Requirements for the HOLD/HOLDA Cycles for EMIFA Module

(1) (see Figure 5-30)

–600

–500, A-600

–720

NO.

UNIT

MIN

MAX

MIN

MAX

th(HOLDAL-HOLDL)

Hold time, HOLD low after HOLDA low

(1)

E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.

Table 5-29. Switching Characteristics Over Recommended Operating Conditions for the HOLD/HOLDA

Cycles for EMIFA Module

(1) (2) (3) (see Figure 5-30)

–600

–500, A-600

–720

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

td(HOLDL-EMHZ)

Delay time, HOLD low to EMIFA Bus high impedance

(4)

td(EMHZ-HOLDAL)

Delay time, EMIF Bus high impedance to HOLDA low

td(HOLDH-EMLZ)

Delay time, HOLD high to EMIF Bus low impedance

td(EMLZ-HOLDAH)

Delay time, EMIFA Bus low impedance to HOLDA high

td(HOLDL-EKOHZ)

Delay time, HOLD low to AECLKOUTx high impedance

(4)

td(HOLDH-EKOLZ)

Delay time, HOLD high to AECLKOUTx low impedance

(1)

E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.

(2)

EMIFA Bus consists of: ACE[3:0], ABE[7:0], AED[63:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and

AAWE/ASDWE/ASWE, ASDCKE, ASOE3, and APDT.

(3)

The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ =

0, ECLKOUTx continues clocking during Hold mode. If

EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 5-30.

(4)

All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the

minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.

EMIFA

Bus

consists

of:

ACE[3:0],

ABE[7:0],

AED[63:0],

AEA[22:3],

AARE/ASDCAS/ASADS/ASRE,

AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE, ASDCKE, ASOE3, and APDT.

The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during

HOLDA. If EKxHZ = 0, ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high

impedance during Hold mode, as shown in Figure 5-30.

Figure 5-30. HOLD/HOLDA Timing for EMIFA

108

DM642 Peripheral Information and Electrical Specifications

TMS320DM642 Datasheet(PDF) 108 Page - Texas Instruments

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