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LAN91C111 Datasheet(PDF) 109 Page - Microchip Technology |
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LAN91C111 Datasheet(HTML) 109 Page - Microchip Technology |
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109 / 125 page ![]() LAN91C111 DS00002276A-page 110 2011-2016 Microchip Technology Inc. FIGURE 14-9: SYNCHRONOUS READ CYCLE - NVLBUS=0 Parameter MIN TYP MAX Units t8 A1-A15, AEN, nBE[3:0] Setup to nADS Rising 8 ns t9 A1-A15, AEN, nBE[3:0] Hold After nADS Rising 5 ns t10 nCYCLE Setup to LCLK Rising 5 ns t11 nCYCLE Hold after LCLK Rising (Non-Burst Mode) 3 ns t16 W/nR Setup to nCYCLE Active 0 ns t20 Data Hold from LCLK Rising (Read) 4 ns t21 nSRDY Delay from LCLK Rising 7 ns t23 nRDYRTN Setup to LCLK Rising 3 ns t24 nRDYRTN Hold after LCLK Rising 3 ns t21 t21 t11 t8 t9 t16 t23 t24 t20 t10 Valid Valid Clock Address, AEN, nBE[3:0] nADS W/nR nCYCLE Read Data nSRDY nRDYRTN |
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