82801AB datasheet(78/414 Pages) INTEL

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Functional Description

5-28

82801AA and 82801AB Datasheet

Cascade Mode

The PIC in the ICH has one master 8259 and one slave 8259 cascaded onto the master through

IRQ2. This configuration can handle up to 15 separate priority levels. The master controls the

slaves through a three bit internal bus. In the ICH, when the master drives 010b on this bus, the

slave controller takes responsibility for returning the interrupt vector. An EOI Command must be

issued twice: once for the master and once for the slave.

Edge and Level Triggered Mode

In ISA systems this mode is programmed using bit 3 in ICW1, which sets level or edge for the

entire controller. In the ICH, this bit is disabled and a new register for edge and level triggered

mode selection, per interrupt input, is included. This is the Edge/Level control Registers ELCR1

and ELCR2.

If an ELCR bit is ‘0’, an interrupt request is recognized by a low to high transition on the

corresponding IRQ input. The IRQ input can remain high without generating another interrupt. If

an ELCR bit is ‘1’, an interrupt request is recognized by a high level on the corresponding IRQ

input and there is no need for an edge detection. The interrupt request must be removed before the

EOI command is issued to prevent a second interrupt from occurring.

In both the edge and level triggered modes, the IRQ inputs must remain active until after the falling

edge of the first internal INTA#. If the IRQ input goes inactive before this time, a default IRQ7

vector is returned.

End of Interrupt Operations

An EOI can occur in one of two fashions: by a command word write issued to the PIC before

returning from a service routine, the EOI command; or automatically when AEOI bit in ICW1 is

set to 1.

Normal End of Interrupt

In Normal EOI, software writes an EOI command before leaving the interrupt service routine to

mark the interrupt as completed. There are two forms of EOI commands: Specific and Non-

Specific. When a Non-Specific EOI command is issued, the PIC clears the highest ISR bit of those

that are set to 1. Non-Specific EOI is the normal mode of operation of the PIC within the ICH, as

the interrupt being serviced currently is the interrupt entered with the interrupt acknowledge. When

the PIC is operated in modes which preserve the fully nested structure, software can determine

which ISR bit to clear by issuing a Specific EOI. An ISR bit that is masked is not be cleared by a

Non-Specific EOI if the PIC is in the Special Mask Mode. An EOI command must be issued for

both the master and slave controller.

Automatic End of Interrupt Mode

In this mode, the PIC automatically performs a Non-Specific EOI operation at the trailing edge of

the last interrupt acknowledge pulse. From a system standpoint, this mode should be used only

when a nested multi-level interrupt structure is not required within a single PIC. The AEOI mode

can only be used in the master controller and not the slave controller.

82801AB Datasheet(PDF) 78 Page - Intel Corporation