82801AB datasheet(61/414 Pages) INTEL

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82801AA and 82801AB Datasheet

5-11

Functional Description

5.3.2

Address Compatibility Mode

Whenever the DMA is operating, the addresses do not increment or decrement through the High

and Low Page Registers. Therefore, if a 24 bit address is 01FFFFh and increments, the next address

is 010000h, not 020000h. Similarly, if a 24 bit address is 020000h and decrements, the next address

is 02FFFFh, not 01FFFFh. This is compatible with the 82C37 and Page Register implementation

used in the PC-AT. This mode is set after CPURST is valid.

5.3.3

Summary of DMA Transfer Sizes

Table 5-7 lists each of the DMA device transfer sizes. The column labeled "Current Byte/Word

Count Register" indicates that the register contents represents either the number of bytes to transfer

or the number of 16-bit words to transfer. The column labeled "Current Address Increment/

Decrement" indicates the number added to or taken from the Current Address register after each

DMA transfer cycle. The DMA Channel Mode Register determines if the Current Address Register

is incremented or decremented.

Address Shifting When Programmed for 16-Bit I/O Count by Words

The ICH maintains compatibility with the implementation of the DMA in the PC AT which used

the 82C37. The DMA shifts the addresses for transfers to/from a 16-bit device count-by-words.

Note that the least significant bit of the Low Page Register is dropped in 16-bit shifted mode. When

programming the Current Address Register (when the DMA channel is in this mode), the Current

Address must be programmed to an even address with the address value shifted right by one bit.

The address shifting is shown in Table 5-8.

NOTE: The least significant bit of the Page Register is dropped in 16-bit shifted mode.

Table 5-7. DMA Transfer Size

DMA Device Date Size And Word Count

Current Byte/Word Count

Current Address

Increment/Decrement

8-Bit I/O, Count By Bytes

Bytes

16-Bit I/O, Count By Words (Address Shifted)

Words

Table 5-8. Address Shifting in 16-bit I/O DMA Transfers

Output

Address

8-Bit I/O Programmed Address

(Ch 0–3)

16-Bit I/O Programmed Address

(Ch 5–7)

(Shifted)

A[16:1]

A[23:17]

A[16:1]

A[23:17]

A[15:0]

A[23:17]

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