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82801AA and 82801AB Datasheet

5-13

Functional Description

5.4

PCI DMA

The ICH provides support for the PC/PCI DMA protocol. PC/PCI DMA uses dedicated REQUEST

and GRANT signals to permit PCI devices to request transfers associated with specific DMA

channels. Upon receiving a request and getting control of the PCI bus, ICH performs a two-cycle

transfer. For example, if data is to be moved from the peripheral to main memory, ICH first reads

data from the peripheral and then write it to main memory. The location in main memory is the

Current Address Registers in the 8237. ICH supports up to 2 PC/PCI REQ/GNT pairs, REQ[A:B]#

and GNT[A:B]#.

A 16-bit register is included in the ICH Function 0 configuration space at offset 90h. It is divided

into seven 2-bit fields that are used to configure the 7 DMA channels. Each DMA channel can be

configured to one of two options:

• LPC DMA

• PC/PCI style DMA using the REQ/GNT signals

It is not possible for a particular DMA channel to be configured for more than one style of DMA;

however, the seven channels can be programmed independently. For example, channel 3 could be

set up for PC/PCI and channel 5 set up for LPC DMA.

The ICH REQ[A:B]# and GNT[A:B]# can be configured for support of a PC/PCI DMA Expansion

agent. The PCI DMA Expansion agent can then provide DMA service or ISA Bus Master service

using the ICH DMA controller. The REQ#/GNT# pair must follow the PC/PCI serial protocol

described below.

5.4.1

PCI DMA Expansion Protocol

The PCI expansion agent must support the PCI expansion Channel Passing Protocol defined in

Figure 5-8 for both the REQ# and GNT# pins.

The requesting device must encode the channel request information as shown above, where

CH0–CH7 are one clock active high states representing DMA channel requests 0–7.

The ICH encodes the granted channel on the GNT# line as shown above, where the bits have the

same meaning as shown in Figure 5-8. For example, the sequence [start, bit 0, bit 1, bit 2]=[0,1,0,0]

grants DMA channel 1 to the requesting device, and the sequence [start, bit 0, bit 1, bit 2]=[0,0,1,1]

grants DMA channel 6 to the requesting device.

Figure 5-8. DMA Serial Channel Passing Protocol

PCICLK

Start

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

Bit0

Bit1

Bit2

Start

REQ#

GNT#

82801AB Datasheet(PDF) 63 Page - Intel Corporation

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