82801AB datasheet(74/414 Pages) INTEL

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Functional Description

5-24

82801AA and 82801AB Datasheet

Acknowledging Interrupts

The processor generates an interrupt acknowledge cycle which is translated by the host bridge into

a PCI Interrupt Acknowledge Cycle to the ICH. The PIC translates this command into two internal

INTA# pulses expected by the 8259 cores. The PIC uses the first internal INTA# pulse to freeze the

state of the interrupts for priority resolution. On the second INTA# pulse, the master or slave sends

the interrupt vector to the processor with the acknowledged interrupt code. This code is based upon

bits [7:3] of the corresponding ICW2 register, combined with three bits representing the interrupt

within that controller.

Table 5-14. Interrupt Status Registers

Bit

Description

IRR

Interrupt Request Register. This bit is set on a low to high transition of the interrupt line in edge

mode, and by an active high level in level mode. This bit is set whether or not the interrupt is

masked. However, a masked interrupt does not generate INTR.

ISR

Interrupt Service Register. This bit is set, and the corresponding IRR bit cleared, when an interrupt

acknowledge cycle is seen, and the vector returned is for that interrupt.

IMR

Interrupt Mask Register. This bit determines whether an interrupt is masked. Masked interrupts do

not generate INTR.

Table 5-15. Content of Interrupt Vector Byte

Master,Slave Interrupt

Bits [7:3]

Bits [2:0]

IRQ7,15

ICW2[7:3]

111

IRQ6,14

110

IRQ5,13

101

IRQ4,12

100

IRQ3,11

011

IRQ2,10

010

IRQ1,9

001

IRQ0,8

000

82801AB Datasheet(PDF) 74 Page - Intel Corporation

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