82801AB datasheet(53/414 Pages) INTEL

53 / 414 page

82801AA and 82801AB Datasheet

5-3

Functional Description

Figure 5-2. Primary Device Status Register Error Reporting Logic

Figure 5-3. Secondary Status Register Error Reporting Logic

AND

D30:F0 BRIDGE_CNT

[Parity Error Response Enable]

D30:F0 BRIDGE_CNT

[SERR# Enable]

PCI Address Parity Error

D30:F0 CMD

[SERR_EN]

D30:F0 PD_STS

[SSE]

AND

Delayed Transaction Timeout

D30:F0 ERR_CMD

[SERR_DTT_EN]

SERR# Pin

D30:F0 BRIDGE_CNT

[SERR# Enable]

D30:F0 ERR_CMD

[SERR_RTA_EN]

Received Target Abort

D30:F0 ERR_STS

[SERR_DTT]

D30:F0 CMD

[SERR_EN]

D30:F0 ERR_STS

[SERR_RTA]

ich pd sts vsd

Note: Shaded area is for ICH (82801AA) only.

AND

D30:F0 SECSTS

[SSE]

D30:F0 BRIDGE_CNT

[SERR# Enable]

PCI Delayed Transaction Timeout

D31:F0 D31_ERR_CFG

[SERR_DTT_EN]

LPC Device Signaling an Error

IOCHK# via SERIRQ

TCO1_STS

[HCSERR_STS]

D31:F0 D31_ERR_CFG

[SERR_RTA_EN]

Received Target Abort

82801AB Datasheet(PDF) 53 Page - Intel Corporation

82801AB Datasheet(HTML) 53 Page - Intel Corporation

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