82801AB datasheet(59/414 Pages) INTEL

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82801AA and 82801AB Datasheet

5-9

Functional Description

5.2.1.9

I/O Cycles

For I/O cycles targeting registers specified in the ICH’s decode ranges, the ICH performs I/O

cycles as defined in the LPC specification. These are 8-bit transfers. If the processor attempts a

16-bit or 32-bit transfer, the ICH breaks it up into multiple 8-bit transfers.

Note:

If the cycle is not claimed by any peripheral (and subsequently aborted), the ICH returns a value of

all 1’s (FFh) to the processor. This is to maintain compatibility with ISA I/O cycles where pull-up

resistors would keep the bus high if no device responds.

5.2.1.10

Bus Master Cycles

The ICH supports Bus Master cycles and requests (using LDRQ#) as defined in the LPC

specification. The ICH has two LDRQ# inputs, and thus supports two separate bus master devices.

It uses the associated START fields for Bus Master 0 (‘0010b’) or Bus Master 1 (‘0011b’).

5.2.1.11

Configuration and ICH Implications

LPC Interface Decoders

To allow the I/O cycles and memory mapped cycles to go to the LPC Interface, the ICH includes

several decoders. During configuration, the ICH must be programmed with the same decode ranges

as the peripheral. The decoders are programmed via the Device 31:Function 0 configuration space.

Bus Master Device Mapping and START Fields

Bus Masters must have a unique START field. In the case of the ICH, which supports 2 bus

masters, it drives 0010 for the START field for grants to bus master #0 (requested via LDRQ[0]#)

and 0011 for grants to bus master #1 (requested via LDRQ[1]#.). Thus no registers are needed to

config the START fields for a particular bus master.

5.3

DMA Operation (D31:F0)

The ICH supports two types of DMA: LPC, and PC/PCI. DMA via LPC is similar to ISA DMA.

LPC DMA and PC/PCI DMA use the ICH’s DMA controller.

The DMA controller has registers that are fixed in the lower 64 KB of I/O space. For PCI

configuration, the controller is configured using registers in the PCI configuration space. These

registers allow configuration of individual channels for use by LPC or PC/PCI DMA.

The DMA circuitry incorporates the functionality of two 82C37 DMA controllers with seven

independently programmable channels (Figure 5-7). DMA Controller 1 (DMA-1) corresponds to

DMA Channels 0–3 and DMA Controller 2 (DMA-2) corresponds to Channels 5–7. DMA Channel

4 is used to cascade the two controllers and defaults to cascade mode in the DMA Channel Mode

(DCM) Register. Channel 4 is not available for any other purpose. In addition to accepting requests

from DMA slaves, the DMA controller also responds to requests that software initiates. Software

may initiate a DMA service request by setting any bit in the DMA Channel Request Register to a 1.

82801AB Datasheet(PDF) 59 Page - Intel Corporation

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