82801AB datasheet(69/414 Pages) INTEL

69 / 414 page

82801AA and 82801AB Datasheet

5-19

Functional Description

Note:

Indicating a ‘0000b’ or ‘1010b’ encoding on the SYNC field of an odd byte of a 16 bit channel

(first byte of a 16 bit transfer) is an error condition.

Note:

The host stops the transfer on the LPC bus as indicated, fills the upper byte with random data on

DMA writes (peripheral to memory), and indicates to the 8237 that the DMA transfer occurred,

incrementing the 8237’s address and decrementing its byte count.

5.5.7

SYNC Field / LDRQ# Rules

Since DMA transfers on LPC are requested through an LDRQ# assertion message, and are ended

through a SYNC field during the DMA transfer, the peripheral must obey the following rule when

initiating back-to-back transfers from a DMA channel.

The peripheral must not assert another message for 8 LCLKs after a deassertion is indicated

through the SYNC field. This is needed to allow the 8237, which typically runs off a much slower

internal clock, to see a message deasserted before it is re-asserted so that it can arbitrate to the next

agent.

Under default operation, the host only performs 8 bit transfers on 8 bit channels and 16 bit transfers

on 16 bit channels.

The method by which this communication between host and peripheral through system BIOS is

performed is beyond the scope of this specification. Since the LPC host and LPC peripheral are

motherboard devices, no “plug-n-play” registry is required.

The peripheral must not assume that the host is able to perform transfer sizes that are larger than

the size allowed for the DMA channel, and is willing to accept a SIZE field that is smaller than

what it may currently have buffered.

To that end, it is recommended that future devices which may appear on the LPC bus, which

require higher bandwidth than 8 bit or 16 bit DMA allow, do so with a bus mastering interface and

not rely on the 8237.

82801AB Datasheet(PDF) 69 Page - Intel Corporation