82801AB datasheet(65/414 Pages) INTEL

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82801AA and 82801AB Datasheet

5-15

Functional Description

5.4.3

DMA Addresses

The memory portion of the cycle generates a PCI memory read or memory write bus cycle, its

address representing the selected memory. The I/O portion of the DMA cycle generates a PCI

I/O cycle to one of the four I/O addresses listed in Table 5-9.

5.4.4

DMA Data Generation

The data generated by PC/PCI devices on I/O reads when they have an active GNT# is on the lower

two bytes of the PCI AD bus. Table 5-10 lists the PCI pins that the data appears on for 8 and 16 bit

channels. Each I/O read results in one memory write, and each memory read results in one

I/O write. If the I/O device is 8 bit, the ICH performs an 8 bit memory write. The ICH does not

assemble the I/O read into a DWord for writing to memory. Similarly, the ICH does not

disassemble a DWord read from memory to the I/O device.

5.4.5

DMA Byte Enable Generation

The byte enables generated by the ICH on I/O reads and writes must correspond to the size of the

I/O device. Table 5-11 defines the byte enables asserted for 8 and 16 bit DMA cycles.

NOTE: For verify cycles the value of the Byte Enables (BEs) is a “don’t care”.

Table 5-9. DMA Cycle vs. I/O Address

DMA Cycle Type

DMA I/O Address

PCI Cycle Type

Normal

00h

I/O Read/Write

Normal TC

04h

I/O Read/Write

Verify

0C0h

I/O Read

Verify TC

0C4h

I/O Read

Table 5-10. PCI Data Bus vs. DMA I/O port size

PCI DMA I/O Port Size

PCI Data Bus Connection

Byte

AD[7:0]

Word

AD[15:0]

Table 5-11. DMA I/O Cycle Width vs. BE[3:0]#

BE[3:0]#

Description

1110b

8-bit DMA I/O Cycle: Channels 0-3

1100b

16-bit DMA I/O Cycle: Channels 5-7

82801AB Datasheet(PDF) 65 Page - Intel Corporation

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