82801AB datasheet(95/414 Pages) INTEL

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82801AA and 82801AB Datasheet

5-45

Functional Description

STPCLK# and CPUSLP# Signals

The ICH power management logic controls these active-low open-drain signals. Refer to

Section 5.12 for more information on the functionality of these signals.

5.11.2

Dual Processor Issues (ICH: 82801AA only)

5.11.2.1

Signal Differences (ICH: 82801AA only)

5.11.2.2

Power Management (ICH: 82801AA only)

In dual processor designs, some of the processor signals are unused or used differently than for

uniprocessor designs.

Table 5-29. DP Signal Differences

Signal

Difference

A20M# / A20GATE

Generally not used, but still supported by ICH.

STPCLK#

Used for S1 State as well as preparation for entry to S3-S5

Also allows for THERM# based throttling (not via ACPI control methods).

Should be connected to both processors.

FERR# / IGNNE#

Generally not used, but still supported by ICH.

Attempting clock control with more than one processor is not feasible, because the MCH does not

provide any indication as to which processor is executing a particular Stop-Grant cycle. Without

this information, there is no way for the 82801AA ICH to know when it is safe to deassert

STPCLK#.

Because the S1 state will have the STPCLK# signal active, the STPCLK# signal can be connected

to both processors. However, for ACPI implementations, the ICH will not support the C2 state for

both processors, since there are not two processor control blocks. The BIOS must indicate that the

ICH only supports the C1 state for dual processor designs. However, the THRM# signal can be

used for overheat conditions to activate thermal throttling.

When entering S1, the ICH asserts STPCLK# to both processors. The ICH will then wait 8 PCI

clocks after receipt of the first Stop-Grant Acknowledge cycle before asserting CPUSLP# (if the

SLP_EN bit is set to 1).

Both processors must immediately respond to the STPCLK# assertion with stop grant acknowledge

cycles before the ICH asserts CPUSLP# in order to meet the processor setup time for CPUSLP#.

Meeting the processor setup time for CPUSLP# is not an issue if both processors are idle when the

system is entering S1. If you cannot guarantee that both processors will be idle, do not enable the

SLP_EN bit. Note that setting SLP_EN to 1 is not required to support S1 in a dual processor

configuration.

S2 is not supported for single or dual processor desktop designs.

In going to the S3, S4, or S5 states, the system will appear to pass through the S1 state, and thus

STPCLK# and SLP# are also used.

During the S3, S4, and S5 states, both processors will lose power. Upon exit from those states, the

processors will have their power restored.

82801AB Datasheet(PDF) 95 Page - Intel Corporation

82801AB Datasheet(HTML) 95 Page - Intel Corporation

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