82801AB datasheet(3/414 Pages) INTEL

3 / 414 page

82801AA and 82801AB

Datasheet

iii

Intel® 82801AA (I CH) and Intel® 82801AB (ICH0)

Features

PCI Bus Interface

— Supports PCI at 33 MHz

— Supports PCI Rev 2.2 Specification

— 133 MByte/sec Maximum Throughput

Integrated IDE Controller

— Independent Timing of Up to 4 Drives

— Supports Ultra ATA/33 Mode

(33 Mbytes/sec)

— PIO Mode 4 Transfers up to 14 Mbytes/s

— Separate IDE Connections for Primary and

Secondary Cables

— Implements Write Ping-Pong Buffer for

faster write performance

USB

— UHCI Implementation With 2 Ports

— Supports Wake-up From Sleeping States

S1-S4

— Supports Legacy Keyboard/Mouse Software

— USB Revision 1.1 Compliant

AC'97 Link for Audio and Telephony CODECs

— AC’97 2.1 Compliant

— 5 Independent Bus Master Logic for PCM In,

PCM Out, Mic Input, Modem In, Modem

Out

— Separate Independent PCI Functions for

Audio and Modem

— Supports wake-up events

Interrupt Controller

— Two Cascaded 82C59

— Integrated I/O APIC Capability

— 15 Interrupts Support in 8259 Mode, 24

Supported in I/O APIC Mode.

— Supports Serial Interrupt Protocol

Timers Based on 82C54

System Timer, Refresh Request, Speaker Tone

Output

3.3 V Operation With 5 V Tolerant Buffers for

IDE and PCI signals.

241 BGA package

GPIO

— TTL, Open-Drain, Inversion

Power Management Logic

— ACPI 1.0 Compliant

— Support for APM-Based Legacy Power

Management for Non-ACPI Implementations

— ACPI Defined Power States (S1, S3, S4, S5)

— ACPI Power Management Timer

— SMI# Generation

— All Registers Readable/Restorable for Proper

Resume from 0 V Suspend States

— PCI PME#

Low Pin count (LPC) Interface

— Allows Connection of Legacy ISA and

X-Bus Devices such as Super I/O

— Supports Two Master/DMA Devices.

Enhanced DMA Controller

— Two Cascaded 8237 DMA Controllers

— PCI DMA: Supports PC/PCI — Includes

Two PC/PCI REQ#/GNT# Pairs

— Supports LPC DMA

— Supports DMA Collection Buffer to Provide

Type-F DMA Performance for All DMA

Channels

Real - Time Clock

— 256-byte Battery-Backed CMOS RAM

— Hardware implementation to indicate

Century Rollover

System TCO Reduction Circuits

— Timers to Generate SMI# and Reset Upon

Detection of locked system

— Timers to Detect Improper Processor Reset

— Integrated Processor Frequency Strap Logic

SM Bus

— Host Interface Allows Processor to

Communicate via SM Bus

— Compatible With Most 2-Wire Components

that are Also I2C compatible

Supports ISA Bus via External PCI-ISA Bridge

Firmware Hub (FWH) Interface

— Master PCI Device Support: up to 6 for the

ICH and up to 4 for the ICH0

— The ICH Supports Ultra ATA/66 Mode (66

Mbytes/sec)

The 82801AA provides Alert On LAN*

Support

The Intel® 82801AA and Intel® 82801AB may contain design defects or errors known as errata which may cause the

products to deviate from published specifications. Current characterized errata are available on request.

This datasheet describes the Intel

® 82801AA and Intel® 82801AB components. Non-shaded areas

describe the functionality of both components.

Shading,as is shown here, indicates differences between the two components.

82801AB Datasheet(PDF) 3 Page - Intel Corporation

82801AB Datasheet(HTML) 3 Page - Intel Corporation

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