82801AB datasheet(32/414 Pages) INTEL

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Signal Description

2-4

82801AA and 82801AB Datasheet

2.4

IDE Interface

SERR#

System Error: SERR# can be pulsed active by any PCI device that detects a system

error condition. Upon sampling SERR# active, the ICH has the ability to generate an

NMI, SMI#, or interrupt.

PME#

PCI Power Management Event: PCI peripherals drive PME# to wake the system from

low-power states S1-S5.

REQ[A]# /

GPIO [0]

REQ[B]#/

REQ[5]# /

GPIO[1]

PC/PCI DMA Request [A:B]: This request serializes ISA-like DMA Requests for the

purpose of running ISA-compatible DMA cycles over the PCI bus. This is used by

devices such as PCI based Super I/O or audio codecs which need to perform legacy

8237 DMA but have no ISA bus.

When not used for PC/PCI requests, these signals can be used as General Purpose

Inputs.

GNT[A]#/

GPIO[16]

GNT[B]#/

GNT[5]# /

GPIO[17]

PC/PCI DMA Acknowledges [A: B]: This grant serializes an ISA-like DACK# for the

purpose of running DMA/ISA Master cycles over the PCI bus. This is used by devices

such as PCI based Super/IO or audio codecs that need to perform legacy 8237 DMA

but have no ISA bus. External pull-up resistors are not required. If external pull-up

resistors are used, they must be tied to the VCC3_3 power rail.

When not used for PC/PCI, these signals can be used as General Purpose Outputs.

Table 2-4. IDE Interface Signals (Sheet 1 of 2)

Name

Type

Description

PDCS1#,

SDCS1#

Primary and Secondary IDE Device Chip Selects for 100 Range: For ATA

command register block. This output signal is connected to the corresponding

signal on the primary or secondary IDE connector.

PDCS3#,

SDCS3#

Primary and Secondary IDE Device Chip Select for 300 Range: For ATA control

primary or secondary IDE connector.

PDA[2:0],

SDA[2:0]

Primary and Secondary IDE Device Address: These output signals are

connected to the corresponding signals on the primary or secondary IDE

connectors. They are used to indicate which byte in either the ATA command block

or control block is being addressed.

PDD[15:0],

SDD[15:0]

I/O

Primary and Secondary IDE Device Data: These signals directly drive the

corresponding signals on the primary or secondary IDE connector.

PDDREQ,

SDDREQ

Primary and Secondary IDE Device DMA Request: These input signals are

directly driven from the DRQ signals on the primary or secondary IDE connector. It

is asserted by the IDE device to request a data transfer, and used in conjunction

with the PCI bus master IDE function and are not associated with any AT

compatible DMA channel.

Table 2-3. PCI Interface Signals (Sheet 3 of 3)

Name

Type

Description

NOTES:

1. For the 82810AA, REQ[B]# can instead be used as the 6th PCI bus request.

2. REQ[5]# (shown in column 1) is only available on the ICH (82801AA).

NOTES:

1. For the 82810AA, GNTB# can also be used as the 6th PCI bus master grant

output.

2. GNT[5]# (shown in column 1) is only available on the ICH (82801AA).

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