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82801AA and 82801AB Datasheet

5-49

Functional Description

5.12.3

SMI#/SCI Generation

Upon any SMI# event taking place, the ICH asserts SMI# to the processor, which causes it to enter

SMM space. SMI# remains active until the EOS bit is set. When the EOS bit is set, SMI# goes

inactive for a minimum of 4 PCICLK. If another SMI event occurs, SMI# is driven active again.

The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating system. In

non-APIC systems (which is the default), the SCI IRQ is routed to one of the 8259 interrupts

(IRQ 9, 10, or 11). The 8259 interrupt controller must be programmed to level mode for that

interrupt.

In systems using the APIC, the SCI can still be routed to IRQ 9, 10, or 11, or it can be instead

routed to one of the APIC interrupts 20:23. In either case, the interrupt generated internally is

active low level. The interrupt remains low until all SCI sources are removed.

Table 5-35 shows which events can cause an SMI# and SCI. Note that some events can be

programmed to cause either an SMI# or SCI. The usage of the event for SCI (instead of SMI#) is

typically associated with an ACPI-based system. Each SMI# or SCI source has a corresponding

enable and status bit.

Table 5-35. Causes of SMI# and/or SCI

Event

SCI

SMI#

Comment

Setting of the BIOS_STS bit

ACPI code in OS sets GBL_RLS bit to cause

BIOS_STS bit active, which causes SMI#.

Setting of the LEGACY_USB_STS

bit

Bit set based on address decode or incoming USB

IRQ.

Write access to APM control register

OS or BIOS writes to the APMC register. SMM handler

clears.

SW SMI# Timer reaches 0

Allows SMM handler to exit temporarily. Another SMI#

occurs about 64 ms later.

Device Trap

Indicates that subsystems may need to be powered

back on.

TCO Event (Includes SERR#)

Can also cause IRQ (other than SCI).

Setting bits in GPE Status Register

with corresponding Enable bit set.

Bits in GPE Status Register include SMBus, TCO,

AC97, RI, PME, USB, THRM and GPIO[n].

Setting of the GBL _STS bit

This bit is set when the BIOS sets the BIOS_RLS bit.

The ACPI handler will clear the bit.

Setting any bit in the PM1_STS

set in the PM1_EN bit.

The SCI/SMI# should be generated, even if waking.

GPIO[n]

If GPIO programmed as input and individually

enabled, Can be Wake event.

Overflow of Power Management

Timer

Time-out every 2.34 seconds. If the timer is enabled,

will cause a) an SCI, if SCI_EN is set, or b) an SMI#, if

SCI_EN is not set.

THRM# signal

The THRM# can cause an SMI# or SCI on either the

rising or falling edge. Causes SCI, if SCI_EN is set;

causes SMI#, if SCI_EN not set.

PWRBTN signal

Can also cause Wake Event

PCI PME# signal

Can also cause Wake Event

Year 2000 Rollover

Does not cause a Wake Event

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