82801AB datasheet(103/414 Pages) INTEL

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82801AA and 82801AB Datasheet

5-53

Functional Description

In case of the PWRBTN# override event, the transition to the S5 is less graceful, since there are no

dependencies on observing Stop-Grant cycles from the processor or on clocks other than the RTC

clock.

Depending on the type of Sleep state desired, the next step the hardware takes is shown in

Table 5-37.

5.12.5.3

Exiting Sleep States

Sleep states (S1-S5) are exited based on Wake events. The Wake events force the system to a full

on state (S0), although some non-critical subsystems will still be shut off and have to be brought

back manually. For example, the hard disk may be shut off during a sleep state and have to be

enabled via a GPIO pin before it can be used.

To enable Wake Events, the possible causes of wake events (and their restrictions) are shown in

Table 5-38.

NOTES:

1. If in the S5 state due to a powerbutton override, the only wake event is power button.

2. This is a wake event from S5 only if the sleep state was entered by setting the SLP_EN and SLP_TYP bits

via software.

Table 5-37. Sleep Types

Sleep Type

Comment

ICH asserts the processor SLP# signal. This lowers the processor’s power consumption. No

snooping is possible in this state.

Not supported.

ICH asserts SLP_S3#. The SLP_S3# signal controls the power to non-critical circuits. Power is

only retained to devices needed to wake from this sleeping state, as well as to the memory.

ICH asserts SLP_S3# and SLP_S5#. The SLP_S5# shuts off the power to the memory

subsystem. Only devices needed to wake from this state should be powered.

Same as S4. ICH asserts SLP_S3# and SLP_S5#. The SLP_S5# signal shuts off the power to

the memory subsystem. Only devices needed to wake from this state should be powered.

Table 5-38. Causes of Wake Events

Cause

States Can

Wake From

How Enabled

RTC Alarm

S1 - S5

(Note 2)

Set RTC_EN bit in PM1_EN Register

Power Button

S1 - S5

(Note 1)

Always enabled as Wake event

GPI[0:n]

S1 - S5

(Note 2)

GPE1_EN register

USB

S1 - S4

Set USB_EN bit in GPE0_EN Register

RI#

S1 - S5

(Note 2)

Set RI_EN bit in GPE0_EN Register

AC97

S1 - S4

Set AC97_EN bit in GPE0_EN Register

PME#

S1 - S5

(Note 2)

Set PME_EN bit in GPE0_EN Register.

SMBALERT#

S1-S4

SMB_WAK_EN in the GPE0 Register

82801AB Datasheet(PDF) 103 Page - Intel Corporation

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