82801AB datasheet(104/414 Pages) INTEL

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Functional Description

5-54

82801AA and 82801AB Datasheet

It is important to understand that the various GPIs have different levels of functionality when used

as wake events. The GPIs that reside in the core power well can only generate wake events from an

S1 state. Also only certain GPIs are “ACPI Compliant,” meaning that their Status and Enable bits

reside in ACPI I/O space. Table 5-39 summarizes the use of GPIs as wake events.

The latency to exit the various Sleep states varies greatly and is heavily dependent on power supply

design. Approximations are shown in Table 5-40. The time indicates from when the Wake event

occurs (signal transition) to when the processor is allowed to start its first cycle (CPURST# goes

inactive). There are very large additional delays for the processor to execute sufficient amounts of

BIOS to invoke the OS (such as coming out of S1-S3) or spinning up the hard drive (such as

coming out of S4 or S5).

5.12.5.4

Sx-G3-Sx, Handling Power Failures

Power failures can occur if the AC power is cut (a real power failure) or if the system is unplugged.

Depending on when the power failure occurs and how the system is designed, different transitions

could occur due to a power failure.

The AFTER_G3 bit provides the ability to program whether or not the system should boot once

power returns after a power loss event. If the policy is to not boot, the system remains in an S5 state

(unless previously in S4). There are only three possible events that wake the system after a power

failure.

1. PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low

(G3 state), the PWRBTN_STS bit is reset. When the ICH exits G3 after power returns

(RSMRST# goes high), the PWRBTN# signal is already high (because Vcc-standby goes high

before RSMRST# goes high) and the PWRBTN_STS bit is 0.

2. RI#: RI# does not have an internal pull-up. This signal should be pulled-up to the suspend well

supply. After recovery from a power failure, the ICH samples RI# after RSMRST# is sampled

deasserted. At that time, RI# will be high (deasserted). The bit that enables RI# as a wake

event is preserved across power failures in the RTC Well supply.

3. RTC Alarm. The RTC_EN bit is in the RTC well and is preserved after a power loss. Like

PWRBTN_STS the RTC_STS bit is cleared when RSMRST# goes low.

Table 5-39. GPI Wake Events

GPI

Power Well

Wake From

Notes

GPI[1:0], GPI[7:5]

Core

GPI[13:8]

Resume

S1-S5

ACPI Compliant

GPIO[28:27]

Resume

S1-S5

Table 5-40. Sleep State Exit Latencies

State

Latency

<1 ms. Based on wake event to STPCLK# high + re-enumeration of PCI bus, USB, CardBus, etc.

Must also add PLL spin-up times

Power Supply ramp + 20 ms

82801AB Datasheet(PDF) 104 Page - Intel Corporation

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