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82801AA and 82801AB Datasheet

5-23

Functional Description

5.7

8259 Interrupt Controllers (PIC) (D31:F0)

The ICH incorporates the functionality of two 8259 interrupt controllers that provide system

interrupts for the ISA compatible interrupts. These interrupts are: system timer, keyboard

controller, serial ports, parallel ports, floppy disk, IDE, mouse, and DMA channels. In addition,

this interrupt controller can support the PCI based interrupts, by mapping the PCI interrupt onto the

compatible ISA interrupt line. Each 8259 core supports 8 interrupts, numbered 0 - 7. Table 5-13

shows how the cores are connected

The ICH cascades the slave controller onto the master controller through master controller

interrupt input 2. This means there are only 15 possible interrupts for the ICH PIC. Interrupts can

individually be programmed to be edge or level, except for IRQ0, IRQ2, IRQ8#, and IRQ13.

Note:

Previous devices internally latched IRQ12 and IRQ1 and required a port 60h read to clear the latch.

The ICH can be programmed to latch IRQ12 or IRQ1 (see bit 11 and bit 12 in General Control

5.7.1

Interrupt Handling

Generating Interrupts

The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each interrupt

level. These bits are used to determine the interrupt vector returned, and status of any other pending

interrupts. Table 5-14 defines the IRR, ISR and IMR.

Table 5-13. Interrupt Controller Core Connections

8259

Input

Typical Interrupt

Source

Connected Pin / Function

Master

Internal

Internal Timer / Counter 0 output

Keyboard

IRQ1 via SERIRQ

Internal

Slave Controller INTR output

Serial Port A

IRQ3 via SERIRQ

Serial Port B

IRQ4 via SERIRQ

Parallel Port / Generic

IRQ5 via SERIRQ

Floppy Disk

IRQ6 via SERIRQ

Parallel Port / Generic

IRQ7 via SERIRQ

Slave

Internal Real Time Clock

Internal RTC

Generic

IRQ9 via SERIRQ

Generic

IRQ10 via SERIRQ

Generic

IRQ11 via SERIRQ

PS/2 Mouse

IRQ12 via SERIRQ

Internal

State Machine output based on processor FERR#

assertion.

Primary IDE cable

IRQ14 from input signal or via SERIRQ

Secondary IDE Cable

IRQ15 from input signal or via SERIRQ

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