82801AB datasheet(33/414 Pages) INTEL

33 / 414 page

82801AA and 82801AB Datasheet

2-5

Signal Description

2.5

Low Pin Count (LPC) Interface

PDDACK#,

SDDACK#

Primary and Secondary IDE Device DMA Acknowledge: These signals directly

drive the DAK# signals on the primary and secondary IDE connectors. Each is

asserted by the ICH to indicate to IDE DMA slave devices that a given data

transfer cycle (assertion of DIOR# or DIOW#) is a DMA data transfer cycle. This

signal is used in conjunction with the PCI bus master IDE function and are not

associated with any AT-compatible DMA channel.

PDIOR# /

(PDWSTB /

PRDMARDY#)

SDIOR# /

(SDWSTB /

SRDMARDY#)

Primary and Secondary Disk I/O Read (PIO and Non-Ultra ATA): This is the

command to the IDE device that it may drive data onto the PDD or SDD lines. Data

is latched by the ICH on the deassertion edge of PDIOR# or SDIOR#. The IDE

device is selected either by the ATA register file chip selects (PDCS1# or SDCS1#,

PDCS3# or SDCS1#) and the PDA or SDA lines, or the IDE DMA acknowledge

(PDDAK# or SDDAK#).

Primary and Secondary Disk Write Strobe (Ultra ATA Writes to Disk): This is

the data write strobe for writes to disk. When writing to disk, ICH drives valid data

on rising and falling edges of PDWSTB or SDWSTB.

Primary and Secondary Disk DMA Ready (Ultra ATA Reads from Disk): This is

the DMA ready for reads from disk. When reading from disk, ICH deasserts

PRDMARDY# or SRDMARDY# to pause burst data transfers.

PDIOW# /

(PDSTOP)

SDIOW# /

(SDSTOP)

Primary and Secondary Disk I/O Write (PIO and Non-Ultra ATA): This is the

command to the IDE device that it may latch data from the PDD or SDD lines. Data

is latched by the IDE device on the deassertion edge of PDIOW# or SDIOW#. The

IDE device is selected either by the ATA register file chip selects (PDCS1# or

SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the IDE DMA

acknowledge (PDDAK# or SDDAK#).

Primary and Secondary Disk Stop (Ultra ATA): ICH asserts this signal to

terminate a burst.

PIORDY /

(PDRSTB /

PWDMARDY#)

SIORDY /

(SDRSTB /

SWDMARDY#)

Primary and Secondary I/O Channel Ready (PIO): This signal will keep the

strobe active (PDIOR# or SDIOR# on reads, PDIOW# or SDIOW# on writes)

longer than the minimum width. It adds wait states to PIO transfers.

Primary and Secondary Disk Read Strobe (Ultra ATA Reads from Disk): When

reading from disk, ICH latches data on rising and falling edges of this signal from

the disk.

Primary and Secondary Disk DMA Ready (Ultra ATA Writes to Disk): When

writing to disk, this is deasserted by the disk to pause burst data transfers.

Table 2-5. LPC Interface Signals

Name

Type

Description

LAD[3:0] /

FWH[3:0]

I/O

LPC Multiplexed Command, Address, Data: Internal pull-ups are provided.

LFRAME# /

FWH[4]

LPC Frame: Indicates the start of an LPC cycle, or an abort.

LDRQ[0]#

LPC Serial DMA/Master Request Inputs: Used to request DMA or bus master

access. Typically connected to external Super I/O device.

LDRQ[1]# /

GPIO[8]

LPC Serial DMA/Master Request Inputs: Second DMA or bus master request. If

LDRQ[1]# is not needed, it can be used as a General Purpose Input.

Table 2-4. IDE Interface Signals (Sheet 2 of 2)

Name

Type

Description

82801AB Datasheet(PDF) 33 Page - Intel Corporation

82801AB Datasheet(HTML) 33 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL