82801AB datasheet(25/414 Pages) INTEL

25 / 414 page

82801AA and 82801AB Datasheet

1-5

Introduction

Compatibility Modules (DMA Controller, Timer/Counters, Interrupt

Controller)

The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven

independently programmable channels. Channels [0:3] are hardwired to 8-bit, count-by-byte

transfers, and channels [5:7] are hardwired to 16-bit, count-by-word transfers. Any two of the

seven DMA channels can be programmed to support fast Type-F transfers.

The ICH supports two types of DMA (LPC and PC/PCI). DMA via LPC is similar to ISA DMA.

LPC DMA and PC/PCI DMA use the ICH’s DMA controller. The PC/PCI protocol allows

PCI-based peripherals to initiate DMA cycles by encoding requests and grants via two PC/PCI

REQ#/GNT# pairs.

LPC DMA is handled through the use of the LDRQ# lines from peripherals and special encodings

on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are supported on the

LPC interface. Channel’s 0 - 3 are 8 bit channels. Channel’s 5 - 7 are 16 bit channels. Channel 4 is

reserved as a generic bus master request.

The timer/counter block contains three counters that are equivalent in function to those found in

one 82C54 programmable interval timer. These three counters are combined to provide the system

timer function, and speaker tone. The 14.31818-MHz oscillator input provides the clock source for

these three counters.

The ICH provides an ISA-Compatible interrupt controller that incorporates the functionality of two

82C59 interrupt controllers. The two interrupt controllers are cascaded so that 14 external and two

internal interrupts are possible. In addition, the ICH supports a serial interrupt scheme.

All of the registers in these modules can be read and restored. This is required to save and restore

system state after power has been removed and restored to the circuit.

Advanced Programmable Interrupt Controller (APIC)

In addition to the standard ISA compatible interrupt controller (PIC) described in the previous

section, the ICH incorporates the Advanced Programmable Interrupt Controller (APIC). While the

standard interrupt controller is intended for use in a uni-processor system, APIC can be used in

either a uni-processor or multi-processor system.

Enhanced Universal Serial Bus (USB) Controller

The USB controller provides enhanced support for the Universal Host Controller Interface (UHCI).

This includes support that allows legacy software to use a USB-based keyboard and mouse. The

ICH is USB Revision 1.1 compliant.

82801AB Datasheet(PDF) 25 Page - Intel Corporation