82801AB datasheet(79/414 Pages) INTEL

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82801AA and 82801AB Datasheet

5-29

Functional Description

5.7.5

Masking Interrupts

Masking on an Individual Interrupt Request

Each interrupt request can be masked individually by the Interrupt Mask Register (IMR). This

IRQ2 on the master controller masks all requests for service from the slave controller.

Special Mask Mode

Some applications may require an interrupt service routine to dynamically alter the system priority

structure during its execution under software control. For example, the routine may wish to inhibit

lower priority requests for a portion of its execution but enable some of them for another portion.

The Special Mask Mode enables all interrupts not masked by a bit set in the Mask Register.

Normally, when an interrupt service routine acknowledges an interrupt without issuing an EOI to

clear the ISR bit, the interrupt controller inhibits all lower priority requests. In the Special Mask

Mode, any interrupts may be selectively enabled by loading the Mask Register with the appropriate

pattern. The special Mask Mode is set by OCW3 where: SSMM=1, SMM=1, and cleared where

SSMM=1, SMM=0.

5.7.6

Steering PCI Interrupts

The ICH can be programmed to allow PIRQA#-PIRQD# to be internally routed to interrupts 3-7,

9-12, 14 or 15. The assignment is programmable through the PIRQx Route Control registers,

located at 60-63h in function 0. One or more PIRQx# lines can be routed to the same IRQx input. If

interrupt steering is not required, the Route Registers can be programmed to disable steering.

The PIRQx# lines are defined as active low, level sensitive to allow multiple interrupts on a PCI

Board to share a single line across the connector. When a PIRQx# is routed to specified IRQ line,

software must change the IRQ's corresponding ELCR bit to level sensitive mode. The ICH

internally inverts the PIRQx# line to send an active high level to the PIC. When a PCI interrupt is

routed onto the PIC, the selected IRQ can no longer be used by an ISA device (through SERIRQ).

However, active low non-ISA interrupts can share their interrupt with PCI interrupts.

82801AB Datasheet(PDF) 79 Page - Intel Corporation