TMS55166 datasheet(42/70 Pages) TI

42 / 70 page

TMS55165, TMS55166, TMS55175, TMS55176

262144 BY 16-BIT MULTIPORT VIDEO RAM

SMVS463 – DECEMBER 1995

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

PARAMETER MEASUREMENT INFORMATION

tc(W)

tw(RL)

tw(RH)

td(RLCH)

td(RLCL)

td(CLRH)

tw(CL)

td(CHRL)

tw(CH)

th(RA)

tsu(RA)

th(RLCA)

tsu(CA)

th(CLCA)

tsu(TRG)

th(RWM)

td(GHD)

tsu(WRH)

tsu(WCH)

th(RLW)

th(CLW)

tsu(WMR)

tsu(DQR)

th(RDQ)

tsu(DWL)†

tw(WL)

th(WLD)†

th(RLD)

RAS

CAS

A0 – A8

WEx

TRG

DQ0 – DQ15

DSF

Row

Column

tsu(SFR)

th(SFR)

th(SFC)

tsu(SFC)

td(CARH)

td(RLCA)

td(CHRL)

th(WLG)

th(RSF)

tsu(rd)

td(CACH)

† In late-write operations, DQ0 – DQ15 are all latched on the first falling edge of WEx. Thus tsu(DWL) and th(WLD) are referenced only to the first

falling edge of WEx.

Figure 33. Late-Write-Cycle Timing (Output-Enable-Controlled Write)

Table 8. Late-Write-Cycle State Table

CYCLE

STATE

CYCLE

Write operation (nonmasked)

Don’t care

Valid data

Write operation with nonpersistent write-per-bit

Write mask

Valid data

Write operation with persistent write-per-bit

Don’t care

Valid data

TMS55166 Datasheet(PDF) 42 Page - Texas Instruments

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