TMS55166 datasheet(10/70 Pages) TI

10 / 70 page

TMS55165, TMS55166, TMS55175, TMS55176

262144 BY 16-BIT MULTIPORT VIDEO RAM

SMVS463 – DECEMBER 1995

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

column-address strobe (CAS)

The falling edge of CAS latches the states of the column address and DSF onto the chip to control DRAM and

transfer functions. CAS also functions as a DRAM output enable.

special-function select (DSF)

DSF is latched on the falling edge of RAS and the falling edge of CAS to determine which functions are invoked

on a particular cycle (see Table 2).

output enable, transfer select (TRG)

TRG selects either DRAM or transfer operation as RAS falls. Holding TRG high on the falling edge of RAS

selects the DRAM operation. Dropping TRG low on the falling edge of RAS selects the transfer operation. TRG

also functions as DRAM output enable.

write enable, write-per-bit select, byte select (WEL, WEU)

WEL and WEU select either the write mode or the read mode in a CAS cycle. Dropping either or both WEL and

WEU low selects the write mode. Holding both WEL and WEU high selects the read mode. Holding either or

both WEL and WEU low on the falling edge of RAS selects the write-per-bit operation. WEL and WEU provide

byte control in DRAM operations. WEL controls the lower byte (DQ0 – DQ7), and WEU controls the upper byte

(DQ8 – DQ15). Byte control can be applied in write cycles, block-write cycles, load-write-mask-register cycles,

and load-color-register cycles.

DRAM data I/O, write mask, column mask (DQ0 – DQ15)

DQ0 – DQ15 function as the DRAM input / output port in DRAM operations. In normal DRAM write cycles, all 16

bits of write data are latched on either the falling edge of CAS or the first falling edge of WEx, whichever occurs

later. Similarly, the DQs are latched as write mask in load-mask-register cycles, as color data in

load-color-register cycles, and as column mask in block-write cycles. In non-persistent write-per-bit cycles, the

DQs are latched as the write mask on the falling edge of RAS.

Data out is in the same polarity as data in. The 3-state output buffer provides direct TTL compatibility (no pullup

resistor required) with a fan-out of one Series 74 TTL load. The outputs are in the high-impedance (floating) state

until RAS, CAS, and TRG have all been brought low in read cycles. For the TMS551x5 devices, the outputs

remain valid until CAS is brought high, TRG is brought high, or WEx is brought low. For the TMS551x6 devices,

the outputs remain valid until both RAS and CAS are brought high, TRG is brought high, or WEx is brought low.

serial clock (SC)

The rising edge of SC increments the internal serial-address counter and accesses serial data at the next SAM

location.

serial enable (SE)

SE functions as the output enable for SQ0 – SQ15 and QSF. SE low enables the serial-data output. SE high

disables the serial-data output. Holding SE high does not disable the serial clock SC. The rising edge of SC

automatically increments the internal serial-address counter regardless of the state of SE.

serial data outputs (SQ0 – SQ15)

SQ0 – SQ15 function as the SAM output port. The 3-state output buffer provides direct TTL compatibility (no

pullup resistors) with a fan-out of one Series 74 TTL load. Serial data is accessed from the SAM on the rising

edge of SC. SE low enables the outputs. The outputs are in the high-impedance (floating) state when disabled.

special-function output (QSF)

QSF is an output pin that indicates which half of the SAM is being accessed. QSF is low when the internal

serial-address counter points to the lower (least significant) 128 bits of the SAM. QSF is high when the internal

serial-address counter points to the higher (most significant) 128 bits of SAM. QSF is in the high-impedance

state when SE is high.

TMS55166 Datasheet(PDF) 10 Page - Texas Instruments

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