TMS55166 datasheet(25/70 Pages) TI

25 / 70 page

TMS55165, TMS55166, TMS55175, TMS55176

262144 BY 16-BIT MULTIPORT VIDEO RAM

SMVS463 – DECEMBER 1995

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

load color register

The load-color-register cycle is performed using normal DRAM write-cycle timing except that DSF is held high

on the falling edges of RAS and CAS. The color register is loaded from pins DQ0 – DQ15, which are latched

on either the first falling edge of WEx or the falling edge of CAS, whichever occurs later. If only one WEx is low,

only the corresponding byte of the color register is loaded. When the color register is loaded, it retains data until

power is lost or until another load-color-register cycle is performed (see Figure 16 and Figure 17).

RAS

CAS

A0 – A8

WEx

TRG

DSF

DQ0 – DQ15

Load-Color-Register Cycle

Block-Write Cycle

(no write mask)

Block-Write Cycle

(nonpersistent write-per-bit)

Legend:

1. Refresh address: A0 – A8 are latched on the falling edge of RAS.

2. Row address: A0 – A8 are latched on the falling edge of RAS.

3. Block address A2 – A8 (TMS5516x) or A3 – A8 (TMS5517x) are latched on the falling edge of CAS.

4. Color data: DQ0 – DQ15 are latched on the falling edge CAS or the first falling edge of WEx, whichever occurs first.

5. Write-mask data: DQ0 – DQ15 are latched on the falling edge RAS.

6. Column-mask data: DQ0 – DQ15 are latched on the falling edge CAS or the first falling edge of WEx, whichever occurs first.

= don’t care

Figure 16. Example of Block Writes

TMS55166 Datasheet(PDF) 25 Page - Texas Instruments