TMS55166 datasheet(53/70 Pages) TI

53 / 70 page

TMS55165, TMS55166, TMS55175, TMS55176

262144 BY 16-BIT MULTIPORT VIDEO RAM

SMVS463 – DECEMBER 1995

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

PARAMETER MEASUREMENT INFORMATION

RAS

CAS

A0 – A8

WEx

TRG

DSF

DQ0 – DQ15

tw(RL)P

td(RLCH)

tc(RDWP)

td(RLCL)

tw(CL)

tw(CH)

td(CLRH)

tw(RH)

td(CHRL)

tsu(CA)

th(RA)

th(RLCA)

tsu(SFR)

th(SFR)

tsu(SFC)

th(SFC)

tsu(rd)

tsu(WMR)

td(CLWL)

td(CAWL)

td(RLWL)

tsu(WCH)

td(GHD)

tdis(G)

Row

Column

Valid Out

td(CARH)

th(CLCA)

ta(C)

td(DCL)

td(DGL)

td(RLCA)

td(CHRL)

th(RDQ)

tsu(DQR)

ta(G)

ta(R)

tsu(TRG)

th(TRG)

tsu(SFC)

ta(C)

td(DCL)

ta(CA)

th(WLD)

ta(CP)

tw(TRG)

tsu(WRH)

th(SFC)

tw(WL)

td(CLGH)

td(DGL)

th(RWM)

td(CLGH)

tw(TRG)

tsu(DWL)

th(WLD)

td(GHD)

td(CACH)

tsu(WCH)

tsu(RA)

tsu(DWL)

NOTE A: A read cycle or a write cycle can be mixed with read-modify-write cycles as long as the read and write timing specifications are not

violated.

Figure 44. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing

Table 13. Enhanced Page-Mode Read-Modify-Write-Cycle State Table

CYCLE

STATE

CYCLE

Write operation (nonmasked)

Don’t care

Valid data

Write operation with nonpersistent write-per-bit

Write mask

Valid data

Write operation with persistent write-per-bit

Don’t care

Valid data

Load-write-mask register on either the first falling edge of

WEx or the falling edge of CAS, whichever occurs later.

Don’t care

Write mask

TMS55166 Datasheet(PDF) 53 Page - Texas Instruments

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