TMS55166 datasheet(20/70 Pages) TI

20 / 70 page

TMS55165, TMS55166, TMS55175, TMS55176

262144 BY 16-BIT MULTIPORT VIDEO RAM

SMVS463 – DECEMBER 1995

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

4-column block write (continued)

Every four adjacent columns makes a block, which results in 128 blocks along one row. Block 0 comprises

columns 0 – 3, block 1 comprises columns 4 – 7, block 2 comprises columns 8 – 11, etc., as shown in Figure 10.

456

511

. . . . . . . . . . . . . . . . . . . . . . . . . . .

Columns

Block 0

Block 1

Block 127

. . . . . . . . . . . . . . . . . . . . . .

One Row of 0 – 511

Figure 10. 4-Column-Block Column-Organization

During 4-column block-write cycles, only the seven most significant column addresses (A2 – A8) are latched on

the falling edge of CAS to decode one of the 128 blocks. Address bits A0 – A1 are ignored. All one-megabit

quadrants have the same block selected.

A block-write cycle is entered in a manner similar to a DRAM write cycle except DSF is held high on the falling

edge of CAS. As in a DRAM write operation, WEL and WEU enable the corresponding lower and upper DRAM

DQ bytes to be written, respectively. The column-mask data is input via the DQs and is latched on either the

falling edge of CAS or the first falling edge of WEx, whichever occurs later. The 16-bit color-data register must

be loaded prior to performing a block write as described below. Refer to the write-per-bit section for details on

use of the write-mask capability, allowing additional performance options.

Example of block write:

block-write column address

= 110000000 (A0 – A8 from left to right)

bit 0

bit 15

color-data register

= 1011

1011

1100

0111

write-mask register

= 1110

1111

1011

column-mask register

= 1111

0000

0111

1010

1st

2nd

3rd

4th

Quad

Column-address bits A0 and A1 are ignored. Block 0 (columns 0 – 3) is selected for all one-megabit quadrants.

The first quadrant has DQ0 – DQ2 written with bits 0 – 2 from the color-data register to all four columns of block

0. DQ3 is not written and retains its previous data due to the write-mask bit 3 being a 0.

The second quadrant (DQ4 – DQ7 ) has all four columns masked off due to the column-mask bits 4 – 7 being 0,

so that no data is written.

The third quadrant (DQ8 – DQ11 ) has its four DQs written with bits 8 – 11 from the color-data register to columns

1 – 3 of its block 0. Column 0 is not written and retains its previous data on all four DQs due to the

column-mask bit 8 being 0.

The fourth quadrant (DQ12 – DQ15 ) has DQ12, DQ14, and DQ15 written with bits 12, 14, and 15 from the

color-data register to column 0 and column 2 of its block 0. DQ13 retains its previous data on all columns due

to the write mask. Columns 1 and 3 retain their previous data on all DQs due to the column mask. If the previous

data for the quadrant was all 0s, the fourth quadrant would contain the data pattern shown in Figure 11 after

the 4-column block-write operation shown in the example.

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