TMS55166 datasheet(12/70 Pages) TI

12 / 70 page

TMS55165, TMS55166, TMS55175, TMS55176

262144 BY 16-BIT MULTIPORT VIDEO RAM

SMVS463 – DECEMBER 1995

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

refresh

CAS-before-RAS (CBR) refresh

CBR refreshes are accomplished when CAS is brought low earlier than RAS. The external row address is

ignored, and the refresh row address is generated internally. Three types of CBR refresh cycles are available.

The CBR refresh (option reset) ends the persistent write-per-bit mode and the stop-point mode. The CBRN (no

reset) and CBRS (no reset and stop point set) refreshes do not end the persistent write-per-bit mode or the

stop-point mode. The 512 rows of the DRAM do not necessarily need to be refreshed consecutively as long as

the entire refresh is completed within the required time period, trf(MA). The output buffers remain in the

high-impedance state during the CBR type refresh cycles regardless of the state of TRG.

hidden refresh

A hidden refresh is accomplished by holding CAS low in the DRAM read cycle and cycling RAS. The output data

of the DRAM read cycle remains valid while the refresh is carried out. Like the CBR refresh, the refreshed row

addresses are generated internally during the hidden refresh.

RAS-only refresh

A RAS-only refresh is accomplished by cycling RAS at every row address. Unless CAS and TRG are low, the

output buffers remain in the high-impedance state to conserve power. Externally generated addresses must be

supplied during RAS-only refresh. Strobing each of the 512 row addresses with RAS causes all bits in each row

to be refreshed.

enhanced page mode (TMS551x5)

Enhanced page mode allows faster memory access by keeping the same row address while selecting random

column addresses. The maximum RAS low time and minimum CAS page cycle time are used to determine the

number of columns that can be accessed.

Unlike conventional page mode, the enhanced page mode allows the TMS551x5 to operate at a higher data

bandwidth. Data retrieval begins as soon as the column address is valid rather than when CAS transitions low.

A valid column address can be presented immediately after the row-address hold time has been satisfied,

usually well in advance of the falling edge of CAS. In this case, data is obtained after ta(C) max ( access time

from CAS low) if ta(CA) max (access time from column address) has been satisfied.

extended data output ( TMS551x6)

The TMS551x6 features extended data output during DRAM accesses. While RAS and TRG are low, the DRAM

output remains valid even when CAS returns high. The output remains valid until WEx is low, TRG is high, or

both CAS and RAS are high (see Figures 1, 2, and 3). The extended data-output mode functions in all read

cycles including DRAM read, page-mode read, and read-modify-write cycles.

Valid Output

tdis(RH)†

RAS

CAS

DQ0 – DQ15

TRG

† See “switching characteristics over recommended ranges of supply voltage and operating free-air temperature” table.

Figure 1. DRAM Read Cycle With RAS-Controlled Output (TMS551x6)

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