TMS55166 datasheet(51/70 Pages) TI

51 / 70 page

TMS55165, TMS55166, TMS55175, TMS55176

262144 BY 16-BIT MULTIPORT VIDEO RAM

SMVS463 – DECEMBER 1995

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

PARAMETER MEASUREMENT INFORMATION

td(CLGH)

RAS

CAS

A0 – A8

WEx

TRG

DSF

DQ0 –

DQ15

tw(RL)P

tw(RH)

td(RLCL)

tw(CL)

tw(CH)

td(CLRH)

td(CHRL)

td(RLCH)

th(RA)

th(RLCA)

th(CLCA)

tc(P)

td(CARH)

th(TRG)

tsu(WMR)

tsu(rd)

ta(G)

ta(R)

ta(CA)

ta(CP)

tdis(G)

tdis(RH)

Row

Column

Data Out

ta(C)

Data In

td(DCL)

td(DGL)

ta(CA)

th(RHrd)

td(RLCA)

tsu(RA)

tsu(TRG)

tsu(CA)

th(SFR)

tsu(SFR)

Data Out

th(CLQ)

td(CACH)

tdis(WL)

NOTE A: A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write- and read-modify-write timing

specifications are not violated and the proper state of DSF is latched on the falling edge of RAS and CAS to select the desired write

mode (normal, block write, etc.).

Figure 42. Extended-Data-Output Read-Cycle Timing (TMS551x6)

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