TMS55166 datasheet(26/70 Pages) TI

26 / 70 page

TMS55165, TMS55166, TMS55175, TMS55176

262144 BY 16-BIT MULTIPORT VIDEO RAM

SMVS463 – DECEMBER 1995

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

load color register (continued)

RAS

CAS

A0 – A8

WEx

TRG

DSF

DQ0 – DQ15

Load-Mask-Register Cycle

Load-Color-Register Cycle

Persistent Write-Per-Bit

Block-Write Cycle

Legend:

1. Refresh address: A0 – A8 are latched on the falling edge of RAS.

2. Row address: A0 – A8 are latched on the falling edge of RAS.

3. Block address A2 – A8 (TMS5516x) or A3 – A8 (TMS5517x) are latched on the falling edge of CAS.

4. Color data: DQ0 – DQ15 are latched on the falling edge CAS or the first falling edge of WEx, whichever occurs first.

5. Write-mask data: DQ0 – DQ15 are latched on the falling edge RAS.

6. Column-mask data: DQ0 – DQ15 are latched on the falling edge CAS or the first falling edge of WEx, whichever occurs first.

= don’t care

Figure 17. Example of a Persistent Block Write

DRAM-to-SAM transfer operation

During the DRAM-to-SAM transfer operation, one half of a row (256 columns) in the DRAM array is selected

to be transferred to the 256-bit serial-data register. The transfer operation is invoked by bringing TRG low and

holding WEx high on the falling edge of RAS. The state of DSF, which is latched on the falling edge of RAS,

determines whether the full-register-transfer operation or the split-register-transfer operation is performed.

Table 5. SAM Function Table

FUNCTION

RAS FALL

CAS

FALL

ADDRESS

DQ0 – DQ15

MNE

FUNCTION

CAS

TRG

WEx†

DSF

RAS

CAS

RAS

CAS

WEx

MNE

CODE

Full-register-transfer read

Row

Addr

Tap

Point

Split-register-transfer read

Row

Addr

Tap

Point

SRT

† Logic L is selected when either or both WEL and WEU are low.

X = don’t care

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