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TMS55166 Datasheet(PDF) 36 Page - Texas Instruments

Part # TMS55166
Description  262144 BY 16-BIT MULTIPORT VIDEO RAM
PDF  70 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS55166 Datasheet(HTML) 36 Page - Texas Instruments

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TMS55165, TMS55166, TMS55175, TMS55176
262144 BY 16-BIT MULTIPORT VIDEO RAM
SMVS463 – DECEMBER 1995
36
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
timing requirements over recommended ranges of supply voltage and operating free-air
temperature†
ALT.
’551xx -60
’551xx - 70
UNIT
SYMBOL
MIN
MAX
MIN
MAX
UNIT
t (P)
Cycle time page mode read write
’551x5
tPC
35
40
ns
tc(P)
Cycle time, page-mode read, write
’551x6
tPC
30
30
ns
tc(rd)
Cycle time, read
tRC
110
130
ns
tc(rdW)
Cycle time, read-modify-write
tRMW
150
175
ns
tc(RDWP)
Cycle time, page-mode read-modify-write
tPRMW
80
90
ns
tc(SC)
Cycle time, serial clock (see Note 9)
tSCC
18
22
ns
tc(TRD)
Cycle time, transfer read
tRC
110
130
ns
tc(W)
Cycle time, write
tWC
110
130
ns
tw(CH)
Pulse duration, CAS high
tCPN
10
10
ns
t (CL)
Pulse duration CAS low (see Note 10)
’551x5
tCAS
10
10 000
10
10 000
ns
tw(CL)
Pulse duration, CAS low (see Note 10)
’551x6
tCAS
17
10 000
20
10 000
ns
tw(GH)
Pulse duration, TRG high
tTP
20
20
ns
tw(RH)
Pulse duration, RAS high
tRP
40
50
ns
tw(RL)
Pulse duration, RAS low (see Note 11)
tRAS
60
10 000
70
10 000
ns
tw(RL)P
Pulse duration, RAS low (page mode)
tRASP
60
100 000
70
100 000
ns
tw(SCH)
Pulse duration, SC high
tSC
5
8
ns
tw(SCL)
Pulse duration, SC low
tSCP
5
8
ns
tw(TRG)
Pulse duration, TRG low
15
20
ns
tw(WL)
Pulse duration, WEx low
tWP
10
10
ns
tsu(CA)
Setup time, column address before CAS low
tASC
0
0
ns
tsu(DCL)
Setup time, data valid before CAS low, early write
tDSC
0
0
ns
tsu(DQR)
Setup time, write mask valid before RAS low,
non-persistent write-per-bit
tMS
0
0
ns
tsu(DWL)
Setup time, data valid before first WEx low, late write
tDSW
0
0
ns
tsu(RA)
Setup time, row address before RAS low
tASR
0
0
ns
tsu(rd)
Setup time, both WEx high before CAS low, read
tRCS
0
0
ns
tsu(SFC)
Setup time, DSF before CAS low
tFSC
0
0
ns
tsu(SFR)
Setup time, DSF before RAS low
tFSR
0
0
ns
tsu(TRG)
Setup time, TRG before RAS low
tTHS
0
0
ns
tsu(WCH)
Setup time, WEx low before CAS high, write
tCWL
15
15
ns
tsu(WCL)
Setup time, first WEx low before CAS low, early write
tWCS
0
0
ns
tsu(WMR)
Setup time, WEx low before RAS low, write-per-bit
tWSR
0
0
ns
tsu(WRH)
Setup time, WEx low before RAS high, write
tRWL
15
15
ns
th(CHrd)
Hold time, both WEx high after CAS high, read (see Note 12)
tRCH
0
0
ns
th(CLCA)
Hold time, column address after CAS low
tCAH
10
10
ns
th(CLD)
Hold time, data valid after CAS low, early write
tDH
15
15
ns
th(CLQ)
Hold time, DQ output after CAS low (TMS551x6)
tDHC
4
5
ns
† Timing measurements are referenced to VIL max and VIH min.
NOTES:
9. Cycle time assumes tt = 3 ns.
10. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. Depending on the user’s transition times, this can require
additional CAS low time [tw(CL)].
11. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the user’s transition times, this can require
additional RAS low time [tw(RL)].
12. Either th(RHrd) or th(CHrd) must be satisfied for a read cycle.



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