TMS55166 datasheet(55/70 Pages) TI

55 / 70 page

TMS55165, TMS55166, TMS55175, TMS55176

262144 BY 16-BIT MULTIPORT VIDEO RAM

SMVS463 – DECEMBER 1995

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

PARAMETER MEASUREMENT INFORMATION

RAS

CAS

A0 – A8

WEx

TRG†

DSF

DQ0 –

DQ15

tw(RL)P

td(RLCH)

td(RLCL)

tw(CL)

tw(CH)

tc(P)

td(CLRH)

td(CHRL)

tw(RH)

tsu(RA)

th(RA)

tsu(CA)

th(CLCA)

td(CARH)

tsu(WMR)

th(RWM)

tsu(SFR)

th(SFR)

th(SFC)

tsu(SFC)

th(SFC)

tsu(WCH)

tw(WL)

tsu(WCH)

tsu(WRH)

tsu(DQR)

th(RDQ)

tsu(DWL)‡

tsu(DCL)‡

th(CLD)‡

th(WLD)‡

th(RLD)

Row

Block Address

A3 – A8

Block Address

A3 – A8

th(TRG)

See Note A

td(RLCA)

td(CHRL)

th(RLCA)

tsu(TRG)

tsu(SFC)

td(CACH)

† In late-write operations, TRG must remain high throughout the entire CAS cycle to assure CAS cycle time tc(P). In early-write operations, the state

of TRG is ignored after the th(TRG) specification is satisfied.

‡ DQ0 – DQ15 are latched on either the falling edge of CAS or the first falling edge of WEx, whichever occurs later. In early-write operations, tsu(DWL)

and th(WLD)arenotapplicable.Inlate-writeoperations,tsu(DCL) and th(CLD)arenotapplicable;tsu(DWL) and th(WLD)arereferencedonlytothe

first falling edge of WEx.

NOTE A: A read cycle or a read-modify-write cycle can be mixed with write cycles as long as read- and read-modify-write timing specifications

are not violated.

Figure 46. Enhanced-Page-Mode Block-Write-Cycle Timing

Table 14. Enhanced-Page-Mode Block-Write-Cycle State Table

CYCLE

STATE

CYCLE

Block-write operation (nonmasked)

Don’t care

Column mask

Block-write operation with nonpersistent write-per-bit

Write mask

Column mask

Block-write operation with persistent write-per-bit

Don’t care

Column mask

TMS55166 Datasheet(PDF) 55 Page - Texas Instruments

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