TMS55166 datasheet(17/70 Pages) TI

17 / 70 page

TMS55165, TMS55166, TMS55175, TMS55176

262144 BY 16-BIT MULTIPORT VIDEO RAM

SMVS463 – DECEMBER 1995

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

persistent write-per-bit

The persistent write-per-bit mode is initiated by performing a load-write-mask-register (LMR) cycle. In the

persistent write-per-bit mode, the write mask is not overwritten but remains valid over an arbitrary number of

write cycles until another LMR cycle is performed, a CBR with reset is executed, or power is removed.

The load-write-mask-register cycle is performed using DRAM write-cycle timing with DSF held high on the falling

edge of RAS and held low on the falling edge of CAS. A binary code is input to the write-mask register via the

DQ pins and latched on either the falling edge of CAS or the first falling edge of WEx, whichever occurs later.

Byte write control can be applied to the write mask during the load-write-mask-register cycle. The persistent

write-per-bit mode can then be used in exactly the same way as the nonpersistent write-per-bit mode except

that the input data on the falling edge of RAS is ignored. When the device is set to the persistent write-per-bit

mode, it remains in this mode and is reset only by a CBR refresh ( option reset ) cycle (see Figure 7).

RAS

CAS

A0 – A8

DSF

Load Write-Mask Register

Persistent Write-Per-Bit

DQ0 –

DQ15

Write-Mask

Write-Data

Mask Data

= 1 : Write to DQ enabled

= 0 : Write to DQ disabled

CBR Refresh (option reset)

WEx

Refresh

Address

Row

Column

Figure 7. Example of a Persistent Write-Per-Bit Operation

TMS55166 Datasheet(PDF) 17 Page - Texas Instruments