Electronic Components Datasheet Search
  English  ▼

X  

TMS55166 Datasheet(PDF) 28 Page - Texas Instruments

Part # TMS55166
Description  262144 BY 16-BIT MULTIPORT VIDEO RAM
PDF  70 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS55166 Datasheet(HTML) 28 Page - Texas Instruments

Back Button TMS55166 Datasheet HTML 24Page - Texas Instruments TMS55166 Datasheet HTML 25Page - Texas Instruments TMS55166 Datasheet HTML 26Page - Texas Instruments TMS55166 Datasheet HTML 27Page - Texas Instruments TMS55166 Datasheet HTML 28Page - Texas Instruments TMS55166 Datasheet HTML 29Page - Texas Instruments TMS55166 Datasheet HTML 30Page - Texas Instruments TMS55166 Datasheet HTML 31Page - Texas Instruments TMS55166 Datasheet HTML 32Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 28 / 70 page
background image
TMS55165, TMS55166, TMS55175, TMS55176
262144 BY 16-BIT MULTIPORT VIDEO RAM
SMVS463 – DECEMBER 1995
28
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
split-register-transfer read
In split-register-transfer operations, the serial-data register is split into halves. The low half contains bits 0 – 127,
and the high half contains bits 128 – 255 (see Figure 20). While one half is being read out of the SAM port, the
other half can be loaded from the memory array.
512
× 512
Memory Array
256 - Bit
Data Register
0
255 256
511
0
255
A8 = 0
A8 = 1
Figure 20. Split-Register-Transfer Read
To invoke a split-register-transfer cycle, DSF is brought high, TRG is brought low, and both are latched at the
falling edge of RAS (see Figure 21). Nine row-address bits (A0 – A8) are also latched at the falling edge of RAS
to select one of the 512 rows available for the transfer. Eight of the nine column-address bits (A0 – A6 and A8)
are latched at the falling edge of CAS. Column-address bit A8 selects which half of the row is to be transferred.
Column-address bit A7 is ignored, and the split-register transfer is internally controlled to select the inactive half.
Column-address bits A0 – A6 select one of 127 tap points in the specified half of SAM. Locations 127 and 255
are not valid tap points in split-register-transfer operations. In stop-point mode, stop-point locations are not valid
tap points in split-register-transfer operations.
Full XFER
RAS
Split XFER
Split XFER
Split XFER
AB
0511
A8 = 0
AB
0
255
SQ
AB
C
0
A7 = 0† 511
A8 = 1
CB
0
255
AB
C
D
0
A7 = 1† 511
A8 = 1
CD
0
255
SQ
AB
C
D
E
0 A7 = 0†
511
A8 = 0
ED
0
255
SQ
SQ
DRAM
SAM
† A7 shown is internally controlled.
Figure 21. Example of a Split-Register-Transfer Read Operation
A full-register transfer must precede the first split-register transfer to ensure proper operation. After the
full-register transfer cycle, the first split-register transfer can follow immediately without any minimum SC clock
requirement (see Figure 22).



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com