TMS55166 datasheet(27/70 Pages) TI

27 / 70 page

TMS55165, TMS55166, TMS55175, TMS55176

262144 BY 16-BIT MULTIPORT VIDEO RAM

SMVS463 – DECEMBER 1995

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

full-register-transfer read

A full-register-transfer operation loads data from a selected half of a row in the DRAM into the SAM. TRG is

brought low and latched at the falling edge of RAS. Nine row-address bits (A0 – A8) are also latched at the falling

edge of RAS to select one of the 512 rows available for the transfer. The nine column-address bits (A0 – A8)

are latched at the falling edge of CAS, where address bit A8 selects which half of the row is transferred. Address

bits A0 – A7 select one of the SAM’s 256 available tap points from which the serial data is read out (see

Figure 18).

512

× 512

Memory Array

256-Bit

Data Register

255 256

511

255

A8 = 0

A8 = 1

Figure 18. Full-Register-Transfer Read

A full-register transfer can be performed in three ways: early load, real-time load (or midline load), or late load.

Each of these offers the flexibility of controlling the TRG trailing edge in the full-register-transfer cycle

(see Figure 19).

Early Load

Real-Time Load

Late Load

RAS

CAS

A0 – A8

TRG

WEx

Row

Tap

Point

Row

Tap

Point

Row

Tap

Point

Tap

Bit

Tap

Bit

Tap

Bit

Old

Data

Old

Data

Old

Data

Old

Data

Old

Data

Figure 19. Example of Full-Register-Transfer Read Operations

TMS55166 Datasheet(PDF) 27 Page - Texas Instruments

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