TMS55166 datasheet(37/70 Pages) TI

37 / 70 page

TMS55165, TMS55166, TMS55175, TMS55176

262144 BY 16-BIT MULTIPORT VIDEO RAM

SMVS463 – DECEMBER 1995

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (continued)†

ALT.

’551xx -60

’551xx - 70

UNIT

SYMBOL

MIN

MAX

MIN

MAX

UNIT

th(CLW)

Hold time, first WEx low after CAS low, early write

tWCH

th(RA)

Hold time, row address after RAS low

tRAH

th(RDQ)

Hold time, write mask valid after RAS low, non-persistent write-per-bit

tMH

th(RHrd)

Hold time, both WEx high after RAS high, read (see Note 12)

tRRH

th(RLCA)

Hold time, column address valid after RAS low (see Note 13)

tAR

th(RLD)

Hold time, data valid after RAS low (see Note 13)

tDHR

th(RLW)

Hold time, WEx low after RAS low, write

tWCR

th(RSF)

Hold time, DSF after RAS low

tFHR

th(RWM)

Hold time, WEx low after RAS low, write-per-bit

tRWH

th(SFC)

Hold time, DSF after CAS low

tCFH

th(SFR)

Hold time, DSF after RAS low

tRFH

th(SHSQ)

Hold time, SQ after SC high

tSOH

th(TRG)

Hold time, TRG after RAS low

tTHH

th(WLD)

Hold time, data valid after first WEx low, late write

tDH

th(WLG)

Hold time, TRG high after WEx low (see Note 14)

tOEH

td(CACH)

Delay time, column address valid to CAS going high

tCAL

td(CAGH)

Delay time, column address to TRG high in real-time-load and late-load

full-register transfer

tATH

td(CARH)

Delay time, column address valid to RAS high

tRAL

td(CASH)

Delay time, column address to first SC high after TRG high, early-load

full-register transfer

tASD

td(CAWL)

Delay time, column address valid to first WEx low, read-modify-write

tAWD

td(CHRL)

Delay time, CAS high to RAS low

tCRP

td(CLGH)

Delay time, CAS low to TRG high, read

td(CLQSF)

Delay time, CAS low to QSF switching, full-register transfer

(see Note 15)

tCQD

td(CLRH)

Delay time, CAS low to RAS going high

tRSH

td(CLRL)

Delay time, CAS low to RAS low, CBR refresh

tCSR

td(CLSH)

Delay time, CAS low to first SC high after TRG high, early-load

full-register transfer

tCSD

td(CLTH)

Delay time, CAS low to TRG high, real-time-load and late-load

full-register transfer

tCTH

td(CLWL)

Delay time, CAS low to first WEx low, read-modify-write (see Note 16)

tCWD

td(CLZ)

Delay time, CAS low to DQ in the low-impedance state

tCLZ

td(DCL)

Delay time, data to CAS low

tDZC

td(DGL)

Delay time, data to TRG low

tDZO

td(GHD)

Delay time, TRG high before data applied at DQ

tOED

† Timing measurements are referenced to VIL max and VIH min.

NOTES: 12. Either th(RHrd) or th(CHrd) must be satisfied for a read cycle.

13. The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference.

14. Output-enable-controlled write. Output remains in the high-impedance state for the entire cycle.

15. TRG must disable the output buffers prior to applying data to the DQ pins.

16. Switching times for QSF output are measured with a load equivalent to 1 TTL load and 30 pF, and output reference level is

VOH / VOL = 2 V/0.8 V.

TMS55166 Datasheet(PDF) 37 Page - Texas Instruments

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