TMS55166 datasheet(52/70 Pages) TI

52 / 70 page

TMS55165, TMS55166, TMS55175, TMS55176

262144 BY 16-BIT MULTIPORT VIDEO RAM

SMVS463 – DECEMBER 1995

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

PARAMETER MEASUREMENT INFORMATION

tw(RH)

RAS

CAS

A0 –

WEx

TRG

DSF

DQ0 –

DQ15

tw(RL)P

td(RLCH)

td(RLCL)

tw(CL)

tw(CH)

tc(P)

tsu(RA)

th(RA)

th(RLCA)

tsu(CA)

th(CLCA)

td(CARH)

tsu(TRG)

tsu(WMR)

th(RWM)

tsu(SFR)

th(SFR)

tsu(SFC)

tsu(WCH)

tsu(WRH)

tsu(DQR)

th(RDQ)

tsu(DCL)†

th(CLD)†

th(WLD)†

th(RLD)

Row

Column

td(CHRL)

td(RSF)

th(TRG)

See Note A

td(RLCA)

td(CLRH)

th(SFC)

tsu(SFC)

th(SFC)

td(CHRL)

tsu(DWL)†

tsu(WCH)

tw(WL)

td(CACH)

† DQ0 – DQ15 are latched on either the falling edge of CAS or the first falling edge of WEx, whichever occurs later. In early-write operations, tsu(DWL)

and th(WLD)arenotapplicable.Inlate-writeoperations,tsu(DCL) and th(CLD)arenotapplicable;tsu(DWL) and th(WLD)arereferencedonlytothe

first falling edge of WEx.

NOTE A: A read cycle or a read-modify-write cycle can be mixed with write cycles as long as read- and read-modify-write timing specifications

are not violated.

Figure 43. Enhanced-Page-Mode Write-Cycle Timing

Table 12. Enhanced-Page-Mode Write-Cycle State Table

CYCLE

STATE

CYCLE

Write operation (nonmasked)

Don’t care

Valid data

Write operation with nonpersistent write-per-bit

Write mask

Valid data

Write operation with persistent write-per-bit

Don’t care

Valid data

Load-write-mask register on either the first falling edge of

WEx or the falling edge of CAS, whichever occurs later.

Don’t care

Write mask

TMS55166 Datasheet(PDF) 52 Page - Texas Instruments

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