TUSB1211 datasheet(6/80 Pages) TI1

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TUSB1211

SLLSE80B – MARCH 2011 – REVISED JUNE 2015

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Pin Functions (continued)

NO.

PIN(1)

NAME

A/D(2)

TYPE(3)

LEVEL(4)

DESCRIPTION

REFCLK clock frequency configuration pin.

CFG

VDDIO

Two frequencies are supported: 19.2 MHz when 0, or 26 MHz

when 1.

I/O

VDD33

DP pin of the USB connector

I/O

VDD33

DM pin of the USB connector

3.3 V internal LDO output. Connect to external filtering

REG3V3

POWER

VDD33

capacitor.

VBAT

POWER

VBAT

Input supply voltage or battery source. Nominally 3.3 V to 4.5 V

VBUS

I/O

VBUS

VBUS pin of the USB connector

I/O

VBUS

Identification (ID) pin of the USB connector

ULPI 60-MHz clock on which ULPI data is synchronized. 2

modes are possible:

Input Mode: CLOCK defaults as an input (this is the default

CLOCK

I/O

VDDIO

clock mode)

Output Mode: When an input clock is detected on REFCLK pin

then CLOCK will change to an output

Active low chip reset pin. Minimum pulse width 100 µs. When

low all digital logic (except 32-kHz logic required for power-up

sequencing and charger detection state-machine) including

RESET_N

VDDIO

registers are reset to their default values. ULPI bus is in “ULPI

Synchronous mode power-up PLL OFF” state as described in

Table 5-5. When high normal USB operation.

STP

VDDIO

ULPI STP input signal

DIR

VDDIO

ULPI DIR output signal

External 1.8-V supply input for digital I/Os. Connect to external

VDDIO

filtering capacitor.

External 1.8-V supply input for digital I/Os. Connect to external

VDDIO

filtering capacitor.

GND

GROUND

GND

Ground

GND

GROUND

GND

Ground

GND

GROUND

GND

Ground

Reference clock input.

Input reference clock frequency must be indicated by CFG pin.

REFCLK

VDDIO

Two frequencies are supported: 19.2 MHz (when CFG = 0), and

26 MHz (when CFG = 1).

HS USB SOF (Start-of-Frame) output clock. (feature controlled

SOF

VDDIO

by SOF_EN bit, disabled and output logic low by default.). HS

USB SOF packet rate is 8 kHz.

—

Not connected

Active-low chip select pin. When high the IC is in power down

CS_N

VDDIO

and ULPI bus is tri-stated. When low (and CS pin is high)

normal operation. Tie to GND if unused.

Active low input pin used to enable Battery Charging Detection

in Dead Battery Charger Detection mode. This pin is ignored in

CHRG_EN_N

VBAT

ACTIVE mode. Connect to GND to activate. Connect to VBAT

when charger detection not required.

VBUS fault detector input used as

EXTERNALVBUSINDICATOR in TUSB1211. The link must

enable VBUS fault detection through the

USEEXTERNALVBUSINDICATOR register bit, and the polarity

FAULT

VBAT

must be set through the INDICATORCOMPLEMENT register

bit. INDICATORPASSTHRU bit can be used to qualify FAULT

with the internal vbusvalid comparator. Connect to GND if not

used. This pin is 5-V tolerant.

When connected to GND then CHRG_DET output pin is active

CHRG_POL

VBAT

low. When connected to VBAT then CHRG_DET output pin is

active high.

Pin Configuration and Functions

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