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TDA2EX Datasheet(PDF) 62 Page - Texas Instruments |
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TDA2EX Datasheet(HTML) 62 Page - Texas Instruments |
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62 / 391 page  62 TDA2EG-17 SPRS969B – AUGUST 2016 – REVISED JUNE 2017 www.ti.com Submit Documentation Feedback Product Folder Links: TDA2EG-17 Terminal Configuration and Functions Copyright © 2016–2017, Texas Instruments Incorporated Table 4-6. EMIF Signal Descriptions (continued) SIGNAL NAME DESCRIPTION TYPE BALL ddr1_a14 EMIF1 Address Bus O AB15 ddr1_a15 EMIF1 Address Bus O AC16 ddr1_d0 EMIF1 Data Bus IO AA23 ddr1_d1 EMIF1 Data Bus IO AC24 ddr1_d2 EMIF1 Data Bus IO AB24 ddr1_d3 EMIF1 Data Bus IO AD24 ddr1_d4 EMIF1 Data Bus IO AB23 ddr1_d5 EMIF1 Data Bus IO AC23 ddr1_d6 EMIF1 Data Bus IO AD23 ddr1_d7 EMIF1 Data Bus IO AE24 ddr1_d8 EMIF1 Data Bus IO AA24 ddr1_d9 EMIF1 Data Bus IO W25 ddr1_d10 EMIF1 Data Bus IO Y23 ddr1_d11 EMIF1 Data Bus IO AD25 ddr1_d12 EMIF1 Data Bus IO AC25 ddr1_d13 EMIF1 Data Bus IO AB25 ddr1_d14 EMIF1 Data Bus IO AA25 ddr1_d15 EMIF1 Data Bus IO W24 ddr1_d16 EMIF1 Data Bus IO W23 ddr1_d17 EMIF1 Data Bus IO U25 ddr1_d18 EMIF1 Data Bus IO U24 ddr1_d19 EMIF1 Data Bus IO W21 ddr1_d20 EMIF1 Data Bus IO T22 ddr1_d21 EMIF1 Data Bus IO U22 ddr1_d22 EMIF1 Data Bus IO U23 ddr1_d23 EMIF1 Data Bus IO T21 ddr1_d24 EMIF1 Data Bus IO T23 ddr1_d25 EMIF1 Data Bus IO T25 ddr1_d26 EMIF1 Data Bus IO T24 ddr1_d27 EMIF1 Data Bus IO P21 ddr1_d28 EMIF1 Data Bus IO N21 ddr1_d29 EMIF1 Data Bus IO P22 ddr1_d30 EMIF1 Data Bus IO P23 ddr1_d31 EMIF1 Data Bus IO P24 ddr1_dqm0 EMIF1 Data Mask O AE23 ddr1_dqm1 EMIF1 Data Mask O W22 ddr1_dqm2 EMIF1 Data Mask O U21 ddr1_dqm3 EMIF1 Data Mask O P25 ddr1_dqs0 Data strobe 0 input/output for byte 0 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading. IO AD22 ddr1_dqsn0 Data strobe 0 invert IO AE22 ddr1_dqs1 Data strobe 1 input/output for byte 1 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading. IO Y24 ddr1_dqsn1 Data strobe 1 invert IO Y25 ddr1_dqs2 Data strobe 2 input/output for byte 2 of the 32-bit data bus. This signal is output to the EMIF1 memory when writing and input when reading. IO V24 ddr1_dqsn2 Data strobe 2 invert IO V25 |
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