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TDA2EX Datasheet(PDF) 72 Page - Texas Instruments |
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TDA2EX Datasheet(HTML) 72 Page - Texas Instruments |
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72 / 391 page  72 TDA2EG-17 SPRS969B – AUGUST 2016 – REVISED JUNE 2017 www.ti.com Submit Documentation Feedback Product Folder Links: TDA2EG-17 Terminal Configuration and Functions Copyright © 2016–2017, Texas Instruments Incorporated Table 4-14. Universal Serial Bus Signal Descriptions (continued) SIGNAL NAME DESCRIPTION TYPE BALL Universal Serial Bus 2 usb2_dm USB2 USB2.0 differential signal pair (negative) IO AC5 usb2_dp USB2 USB2.0 differential signal pair (positive) IO AB6 usb2_drvvbus USB2 Drive VBUS signal O AA6 Universal Serial Bus 3 usb3_ulpi_d0 USB3 - ULPI 8-bit data bus IODS R2, W2 usb3_ulpi_d1 USB3 - ULPI 8-bit data bus IODS AA3, R1 usb3_ulpi_d2 USB3 - ULPI 8-bit data bus IO AA2, N2 usb3_ulpi_d3 USB3 - ULPI 8-bit data bus IO P2, Y4 usb3_ulpi_d4 USB3 - ULPI 8-bit data bus IO N1, Y1 usb3_ulpi_d5 USB3 - ULPI 8-bit data bus IO P1, Y2 usb3_ulpi_d6 USB3 - ULPI 8-bit data bus IO N3, Y6 usb3_ulpi_d7 USB3 - ULPI 8-bit data bus IO N4, Y5 usb3_ulpi_nxt USB3 - ULPI next I P3, Y3 usb3_ulpi_dir USB3 - ULPI bus direction I AA1, P4 usb3_ulpi_stp USB3 - ULPI stop O AA4, T5 usb3_ulpi_clk USB3 - ULPI functional clock I AB1, T4 (1) Signals are enabled by selecting the correct field in the PCIE_B1C0_MODE_SEL register. There are no CTRL_CORE_PAD* register involved. 4.3.14 PCIe NOTE For more information, see the Serial Communication Interfaces / PCIe Controllers and the Shared PHY Component Subsystems / PCIe Shared PHY Susbsytem sections of the device TRM. Table 4-15. PCIe Signal Descriptions SIGNAL NAME DESCRIPTION TYPE BALL pcie_rxn0 PCIe1_PHY_RX Receive Data Lane 0 (negative) - mapped to PCIe_SS1 only. IDS AE6 pcie_rxp0 PCIe1_PHY_RX Receive Data Lane 0 (positive) - mapped to PCIe_SS1 only. IDS AD7 pcie_txn0 PCIe1_PHY_TX Transmit Data Lane 0 (negative) - mapped to PCIe_SS1 only. ODS AE8 pcie_txp0 PCIe1_PHY_TX Transmit Data Lane 0 (positive) - mapped to PCIe_SS1 only. ODS AD9 pcie_rxn1 PCIe2_PHY_RX Receive Data Lane 1 (negative) - mapped to either PCIe_SS1 (dual lane- mode) or PCIe_SS2 (single lane- mode) IDS AE5 pcie_rxp1 PCIe2_PHY_RX Receive Data Lane 1 (positive) - mapped to either PCIe_SS1 (dual lane- mode) or PCIe_SS2 (single lane- mode) IDS AD6 pcie_txn1 PCIe2_PHY_TX Transmit Data Lane 1 (negative) - mapped to either PCIe_SS1 (dual lane- mode) or PCIe_SS2 (single lane- mode) ODS AE3 pcie_txp1 PCIe2_PHY_TX Transmit Data Lane 1 (positive) - mapped to either PCIe_SS1 (dual lane- mode) or PCIe_SS2 (single lane- mode) ODS AD4 ljcb_clkn PCIe1_PHY / PCIe2_PHY shared Reference Clock Input / Output Differential Pair (negative) IODS AB9 ljcb_clkp PCIe1_PHY / PCIe2_PHY shared Reference Clock Input / Output Differential Pair (positive) IODS AC8 |
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