DAC38RF80 datasheet(40/155 Pages) TI1

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DACCLK+

DACCLK-

DACCLKSE

SEL_EXTCLK_DIFFSE

DAC PLL

Predivider

SERDES_REFCLK_SEL

divider

SERDES_REFCLK_DIV

SERDES_REFCLK_PREDIV

SERDES

PLL

REFCLK

DAC38RF80, DAC38RF83, DAC38RF84

DAC38RF85, DAC38RF90, DAC38RF93

SLASEA3C – DECEMBER 2016 – REVISED JULY 2017

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DAC38RF83 DAC38RF93

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8.3.2 SerDes Rate

The DAC38RFxx has eight configurable JESD204B serial lanes. The highest speed of each SerDes lane is 12.5

Gbps. Because the primary operating frequency of the SerDes is determined by its reference clock and PLL

multiplication factor, there is a limit on the lowest SerDes rate supported. To support lower speed application,

each receiver should be configured to operate at half, quarter or eighth of the full rate via field RATE in register

SRDS_CFG2 (8.5.87). Refer to Table 2 for details.

Table 2. Lane Rate Selection

RATE

EFFECT

Full rate. Four data samples taken per SerDes PLL output clock cycle.

Half rate. Two data samples taken per SerDes PLL output clock cycle.

Quarter rate. One data samples taken per SerDes PLL output clock cycle.

Eighth rate. One data samples taken every two SerDes PLL output clock cycles.

8.3.3 SerDes PLL

The DAC38RFxx has two integrated PLLs, one PLL is to provide the clocking of DAC; the other PLL is to provide

the clocking for the high speed SerDes. The reference frequency of the SerDes PLL can be in the range of 100-

800 MHz nominal, and 300-800 MHz optimal. The reference frequency is derived from DACCLK divided down by

the value in field SerDes_REFCLK_DIV in register SRDS_CLK_CFG (8.5.84), as shown in Figure 52. Field

SerDes_CLK_SEL in register SRDS_CLK_CFG (8.5.84) determines if the DACCLK input or DAC PLL output is

used as the source of the SerDes PLL reference. If the DACCLK input is used, a pre-divider set by field

SerDes_REFCLK_PREDIV in register SRDS_CLK_CFG (8.5.84) should be used to reduce the frequency of the

DACCLK.

Figure 52. Reference Clock of SerDes PLL

During normal operation, the clock generated by PLL is 4-25 times the reference frequency, according to the

multiply factor selected via the field MPY] in register SRDS_PLL_CFG (8.5.85). In order to select the appropriate

multiply factor and reference clock frequency, it is first necessary to determine the required PLL output clock

frequency. The relationship between the PLL output clock frequency and the lane rate is determined by field

RATE in register SRDS_CFG2 (8.5.87) is shown in Table 3. Having computed the PLL output frequency, the

reference frequency can be obtained by dividing this by the multiply factor specified via MPY.

DAC38RF80 Datasheet(PDF) 40 Page - Texas Instruments

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